[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill-nvidia-jetson-customize-usb":3,"mdc-k6q6jn-key":33,"related-repo-nvidia-jetson-customize-usb":1215,"related-org-nvidia-jetson-customize-usb":1321},{"slug":4,"name":4,"fn":5,"description":6,"org":7,"tags":11,"stars":22,"repoUrl":23,"updatedAt":24,"license":25,"forks":26,"topics":27,"repo":28,"sourceUrl":31,"mdContent":32},"jetson-customize-usb","configure Jetson USB port settings","Enable\u002Fdisable Jetson USB2\u002FUSB3 SS ports via kernel-DT overlay. Do NOT use for UPHY lane allocation or ODMDATA edits.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},"nvidia","NVIDIA","https:\u002F\u002Fpexgzepcugksgbtrxkhf.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Forg-logos\u002Fnvidia.png",[12,16,19],{"name":13,"slug":14,"type":15},"Hardware","hardware","tag",{"name":17,"slug":18,"type":15},"Linux","linux",{"name":20,"slug":21,"type":15},"Engineering","engineering",2473,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills","2026-07-14T05:26:10.040804","Apache-2.0",281,[],{"repoUrl":23,"stars":22,"forks":26,"topics":29,"description":30},[],"AI agent skills published by NVIDIA","https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills\u002Ftree\u002FHEAD\u002Fskills\u002Fjetson-customize-usb","---\nname: jetson-customize-usb\ndescription: Enable\u002Fdisable Jetson USB2\u002FUSB3 SS ports via kernel-DT overlay. Do NOT use for UPHY lane allocation or ODMDATA edits.\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - bsp\n    - phase-2\n    - io\n    - usb\n  domain: meta\n---\n\n# Customize USB (per-port enable \u002F disable \u002F role)\n\n## Purpose\n\nEnable, disable, or change the role of USB2 \u002F USB3 SS ports on a\nJetson Thor (Tegra264) or Orin (Tegra234) custom carrier. Captures\nper-port wiring (role, max speed, VBUS-EN \u002F OC GPIOs, CC1\u002FCC2 GPIOs\nfor Type-C, USB3 SS UPHY lane), resolves the SS to USB2 companion\ngraph from the in-tree DTB, then renders a self-contained kernel-DT\noverlay that flips every port action in three places in lockstep\n(lane status, port status, host xHCI `phys` + `phy-names`).\n\nUPHY lane allocation belongs to `jetson-customize-uphy`. No ODMDATA\nedit. Output is one commit to the composite custom overlay `.dts` in\nthe `bsp_sources\u002F` hardware repo.\n\n## Prerequisites\n\n- Active profile with `reference_devkit:` + `custom_carrier:` blocks.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` exists\n  (`\u002Fjetson-init-source`).\n- `\u002Fjetson-derive-carrier` has run — carrier flash-conf fork in the\n  overlay tracker.\n- `\u002Fjetson-customize-uphy` has run when any enabled USB3 SS port\n  needs a non-stock UPHY lane allocation. Its JSON sidecar at\n  `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-uphy.json`\n  is consulted for SS lane allocation.\n- Source-of-truth docs: Adaptation Guide §\"Port the Universal Serial\n  Bus\", Module Design Guide §USB, SoC TRM (xusb block).\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** Refuse the run\n  if either is missing — per-port routing (VBUS-EN \u002F OC \u002F CC GPIOs, SS\n  lane wiring, hub fan-out) on a custom carrier cannot be guessed.\n  Reference-devkit-only profiles skip this check.\n- `dtc`, `fdtoverlay` on PATH.\n\n## Overview\n\nUSB on Tegra spans three IP surfaces: the `xusb_padctl` block (USB2\nOTG + USB3 SS PHYs), the `tegra-xusb` xHCI host controller, and an\noptional `tegra-xudc` device controller attached to the single\nOTG-capable USB2 port (`usb2-0`).\n\n**A per-port flip MUST touch three kernel-DT places in lockstep.**\nAnything less crashes the host xHCI probe and leaves `lsusb` empty\non every port (collateral damage to stock-okay ports):\n\n| # | Place | Path | What it controls |\n|---|---|---|---|\n| 1 | **Lane (PHY provider)** | `xusb_padctl\u002Fpads\u002Fusb\u003C2\\|3>\u002Flanes\u002Fusb\u003C2\\|3>-N` | SS \u002F OTG PHY hardware-binding. `status=\"disabled\"` then lane stops providing a PHY. |\n| 2 | **Port (controller-binding)** | `xusb_padctl\u002Fports\u002Fusb\u003C2\\|3>-N` | Per-port mode (host\u002Fdevice\u002Fotg), companion link, VBUS \u002F OC \u002F CC pin refs. `status=\"disabled\"` then port removed from user-facing topology. |\n| 3 | **Host xHCI phys-list** | `bus@0\u002Fusb@\u003Caddr>.phys` + `.phy-names` | Array of phandles + names the xHCI driver iterates. A ref to a disabled PHY returns `-ENODEV` and aborts the whole host probe. |\n\nNVIDIA's stock-disabled `usb3-3` in the Thor base DTB is the canonical\npattern — all three places flipped in lockstep.\n\n**Two extra rules ride on top of the three-place pattern:**\n\n- **Rule A — lane + port pairing.** Lane (place 1) and matching port\n  (place 2) MUST flip together.\n- **Rule B — companion cascade.**\n  `xusb_padctl\u002Fports\u002Fusb3-N.nvidia,usb2-companion` references a USB2\n  port phandle. Disabling that USB2 without cascading to its SS\n  companion then `tegra-xusb: failed to enable PHYs: -19`.\n\n**Agentic, not table-driven** — every port, controller, lane,\ncompanion link, phandle, and `__symbols__` lookup is resolved at\nruntime from docs + DTB + carrier pinmap + schematic.\n\n## When to invoke\n\n- The user says \"enable USB\", \"disable USB hub\", \"configure USB3 SS\",\n  \"set USB role\", \"wire VBUS-EN\", \"tegra-xusb \u002F xudc \u002F dr_mode\", or\n  asks to bring up \u002F take down a USB controller on a custom carrier.\n- A USB receptacle on the carrier doesn't enumerate after flash, OR\n  collateral USB damage (`lsusb` empty after a previous\n  jetson-customize-usb attempt) needs to be fixed.\n- `jetson-customize-uphy` re-allocated UPHY lanes affecting USB3 SS\n  ports and per-port DT now needs to follow.\n\n## Procedure (summary)\n\nThe full step-by-step procedure lives in `references\u002Fprocedure.md`.\n\n1. **Step 1** — resolve active target + open source-of-truth docs.\n2. **Step 2** — build the USB topology + companion graph from the\n   in-tree DTB.\n3. **Step 3** — `AskUserQuestion` for port(s) to enable \u002F disable;\n   surface companion cascade + on-carrier hub fan-out explicitly.\n4. **Step 4** — per-port verify (module + carrier + UPHY lane) and\n   capture wiring (VBUS-EN \u002F OC \u002F CC GPIOs via `pin_verifier.py`).\n5. **Step 5** — render the kernel-DT overlay using the three-place\n   pattern, append fragments (`usb:padctl`, `usb:xhci`, optional\n   `usb:xudc`) to the composite custom overlay `.dts`, run\n   `fdtoverlay` + the three post-merge invariants, commit to\n   `bsp_sources\u002F`.\n6. **Step 6** — write run-state JSON sidecar (shape in\n   `references\u002Frun-state-sidecar.md`), emit headline, then drive the\n   downstream next-step chain via sequential `AskUserQuestion` prompts\n   per `references\u002Fprocedure.md` Step 6. Never substitute a printed\n   \"Next step: …\" line for the prompts.\n\nSee `references\u002Fgotchas.md` for the load-bearing failure modes.\n\n## Limitations\n\n- Owns kernel-DT overlay only. ODMDATA does not expose a per-port\n  USB `status` knob; do not edit it.\n- Does NOT allocate UPHY lanes — `jetson-customize-uphy` owns that.\n  Refuse to commit an SS-enable until uphy run-state shows the lane\n  allocated.\n- Does NOT directly patch the pinmux DTSI — routes SFIO mismatches\n  to `\u002Fjetson-customize-pinmux set-pin`.\n- Does NOT compile the `.dtbo` or register `OVERLAY_DTB_FILE+=` —\n  `\u002Fjetson-build-source` owns build + flash-conf registration.\n- Tegra platform invariant: only `usb2-0` is OTG-capable; `xudc`\n  attaches there only. All other USB2 ports and all USB3 SS ports\n  are host-only.\n\n## Troubleshooting\n\n- **Empty `lsusb` on every port, USB-eth at 192.168.55.1 still up:**\n  host xHCI bailed; three-place lockstep was broken. Inspect merged\n  DTB; verify post-merge invariants in `references\u002Fprocedure.md`\n  Step 5d.\n- **`tegra-xusb: failed to enable PHYs: -19`:** companion cascade\n  (Rule B) violated — a USB2 was disabled without its SS companion.\n- **`no port found` or `Requested PHY is disabled`:** Rule A\n  violated — lane status and port status are mismatched.\n- **`FDT_ERR_NOTFOUND` from `fdtoverlay`:** a fragment used\n  `target = \u003C&label>` for a node whose label is not in\n  `__symbols__` (typical for host xHCI \u002F `tegra-xudc`). Switch to\n  `target-path = \"\u002Fbus@0\u002Fusb@\u003Caddr>\"`.\n- **dtc warning `phys_property: cell 0 is not a phandle reference`:**\n  benign; expected when using raw integer phandles in the host phys\n  override.\n- **Port boots but VBUS never asserts:** `vbus-supply` references a\n  regulator parent node that does not exist. Ensure the fixed\n  regulator node is present before referencing it.\n- **xHCI binds the wrong port at boot:** host `phys` element order\n  was not preserved. Only elide disabled entries; never reorder\n  kept ones.\n\n## References\n\n- `references\u002Fprocedure.md` — full step-by-step procedure.\n- `references\u002Fgotchas.md` — load-bearing failure modes.\n- `references\u002Frun-state-sidecar.md` — run-state JSON shape.\n- `references\u002Fusb-architecture.md` — Tegra USB IP architecture\n  notes (`xusb_padctl`, `tegra-xusb`, `xudc`).\n- `references\u002Fusb-dt-bindings.md` — USB DT binding cheatsheet\n  (lane \u002F port \u002F phys-list shapes).\n- `..\u002F..\u002Fscripts\u002Fpin_verifier.py` — shared HSIO pin verifier.\n- `..\u002F..\u002Freferences\u002Fplatform_template.yaml` — `documents:` block\n  consumed by Step 1.\n- `..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md` — overlay edit\n  protocol.\n- `..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md` — composite\n  overlay append protocol.\n- `..\u002Fjetson-customize-uphy\u002FSKILL.md` — sibling skill that owns\n  UPHY lane allocation.\n- `..\u002Fjetson-customize-pinmux\u002FSKILL.md` — sibling skill for\n  VBUS-EN \u002F OC \u002F CC SFIO fixes.\n- `..\u002Fjetson-derive-carrier\u002FSKILL.md` — must run first.\n- `..\u002Fjetson-init-source\u002FSKILL.md` — produces the overlay tracker\n  + `bsp_sources` repo.\n",{"data":34,"body":45},{"name":4,"description":6,"version":35,"license":25,"metadata":36},"0.0.1",{"data-classification":37,"author":38,"tags":39,"domain":44},"public","Jetson Team",[40,41,42,43],"bsp","phase-2","io","usb","meta",{"type":46,"children":47},"root",[48,57,64,87,116,122,253,259,295,313,471,484,492,529,547,553,583,589,601,745,758,764,853,859,1027,1033],{"type":49,"tag":50,"props":51,"children":53},"element","h1",{"id":52},"customize-usb-per-port-enable-disable-role",[54],{"type":55,"value":56},"text","Customize USB (per-port enable \u002F disable \u002F role)",{"type":49,"tag":58,"props":59,"children":61},"h2",{"id":60},"purpose",[62],{"type":55,"value":63},"Purpose",{"type":49,"tag":65,"props":66,"children":67},"p",{},[68,70,77,79,85],{"type":55,"value":69},"Enable, disable, or change the role of USB2 \u002F USB3 SS ports on a\nJetson Thor (Tegra264) or Orin (Tegra234) custom carrier. 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install, deploy, run, validate, troubleshoot, or stop NVIDIA AI-Q Blueprint infrastructure.\n",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1240,1243,1246],{"name":1241,"slug":1242,"type":15},"Deployment","deployment",{"name":1244,"slug":1245,"type":15},"Infrastructure","infrastructure",{"name":9,"slug":8,"type":15},"2026-07-14T05:29:06.667109",{"slug":1249,"name":1249,"fn":1250,"description":1251,"org":1252,"tags":1253,"stars":22,"repoUrl":23,"updatedAt":1261},"aiq-research","conduct deep research with AI-Q","Use when asked to run deep research or AI-Q research through a reachable NVIDIA AI-Q Blueprint backend.\n",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1254,1257,1258],{"name":1255,"slug":1256,"type":15},"Agents","agents",{"name":9,"slug":8,"type":15},{"name":1259,"slug":1260,"type":15},"Research","research","2026-07-14T05:28:06.816956",{"slug":1263,"name":1263,"fn":1264,"description":1265,"org":1266,"tags":1267,"stars":22,"repoUrl":23,"updatedAt":1273},"amc-run-sample-calibration","run AMC sample dataset calibration","Run end-to-end calibration on the shipped sample dataset (sdg_08_2_sample_data_010926.zip) against a running AMC microservice. Use when user says 'test sample dataset', 'run sample calibration', 'verify AMC install', or 'launch and test'.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1268,1269,1270],{"name":1224,"slug":1225,"type":15},{"name":9,"slug":8,"type":15},{"name":1271,"slug":1272,"type":15},"Testing","testing","2026-07-17T05:29:03.913266",{"slug":1275,"name":1275,"fn":1276,"description":1277,"org":1278,"tags":1279,"stars":22,"repoUrl":23,"updatedAt":1290},"amc-run-video-calibration","calibrate video datasets with AutoMagicCalib","Calibrate a new dataset from pre-recorded video files via the AutoMagicCalib REST API. Use when user has local MP4s and says 'calibrate my videos', 'run AMC on these videos', or similar. For RTSP\u002Flive streams, use amc-run-rtsp-calibration instead.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1280,1283,1286,1287],{"name":1281,"slug":1282,"type":15},"Automation","automation",{"name":1284,"slug":1285,"type":15},"Imaging","imaging",{"name":9,"slug":8,"type":15},{"name":1288,"slug":1289,"type":15},"Video","video","2026-07-17T05:28:53.905004",{"slug":1292,"name":1292,"fn":1293,"description":1294,"org":1295,"tags":1296,"stars":22,"repoUrl":23,"updatedAt":1305},"amc-setup-calibration-stack","deploy AutoMagicCalib microservice with Docker","Launch AutoMagicCalib microservice and web UI from NGC release images via Docker Compose. Use when user says 'deploy auto calibration', 'launch auto calibration', 'launch AMC', 'start MS+UI', or 'set up auto-magic-calib'. Requires NGC API key.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1297,1298,1301,1302],{"name":1241,"slug":1242,"type":15},{"name":1299,"slug":1300,"type":15},"Docker","docker",{"name":9,"slug":8,"type":15},{"name":1303,"slug":1304,"type":15},"Operations","operations","2026-07-17T05:28:56.913999",{"slug":1307,"name":1307,"fn":1308,"description":1309,"org":1310,"tags":1311,"stars":22,"repoUrl":23,"updatedAt":1319},"cudaq-guide","develop quantum applications with CUDA-Q","CUDA-Q onboarding guide for installation, test programs, GPU simulation, QPU hardware, and quantum applications.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1312,1313,1316],{"name":9,"slug":8,"type":15},{"name":1314,"slug":1315,"type":15},"Quantum Computing","quantum-computing",{"name":1317,"slug":1318,"type":15},"Simulation","simulation","2026-07-14T05:26:58.898253",305,{"items":1322,"total":1473},[1323,1341,1357,1368,1380,1394,1407,1421,1432,1441,1455,1464],{"slug":1324,"name":1324,"fn":1325,"description":1326,"org":1327,"tags":1328,"stars":1338,"repoUrl":1339,"updatedAt":1340},"nemoclaw-user-guide","retrieve NemoClaw documentation and configuration","Guides human users' AI agents to the NemoClaw docs MCP server and canonical Fern documentation in Markdown form. Use when users ask how to install, configure, operate, troubleshoot, secure, or learn NemoClaw with an AI coding assistant. Trigger keywords - nemoclaw docs, use nemoclaw with ai agent, nemoclaw mcp docs, nemoclaw install help, nemoclaw quickstart, nemoclaw markdown docs, llms.txt, agent skills.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1329,1332,1335],{"name":1330,"slug":1331,"type":15},"Documentation","documentation",{"name":1333,"slug":1334,"type":15},"MCP","mcp",{"name":1336,"slug":1337,"type":15},"Search","search",21777,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FNemoClaw","2026-07-20T06:00:01.461044",{"slug":1342,"name":1342,"fn":1343,"description":1344,"org":1345,"tags":1346,"stars":1354,"repoUrl":1355,"updatedAt":1356},"mcore-build-and-dependency","manage Megatron-LM development environments","Container-based dev environment setup and dependency management for Megatron-LM. Covers acquiring and launching the CI container, uv package management, and updating uv.lock.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1347,1350,1351],{"name":1348,"slug":1349,"type":15},"Containers","containers",{"name":1241,"slug":1242,"type":15},{"name":1352,"slug":1353,"type":15},"Python","python",17049,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FMegatron-LM","2026-07-27T06:06:11.249662",{"slug":1358,"name":1358,"fn":1359,"description":1360,"org":1361,"tags":1362,"stars":1354,"repoUrl":1355,"updatedAt":1367},"mcore-bump-base-image","update NVIDIA PyTorch base images","Bump the NVIDIA PyTorch base image (`nvcr.io\u002Fnvidia\u002Fpytorch:YY.MM-py3`) used by Megatron-LM CI. Covers the two pin sites (GitHub CI in `docker\u002F.ngc_version.dev` and GitLab CI in `.gitlab\u002Fstages\u002F01.build.yml`), the post-bump CI loop (re-run functional tests, refresh golden values, mark broken tests), and the gotchas that bit PRs",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1363,1366],{"name":1364,"slug":1365,"type":15},"CI\u002FCD","ci-cd",{"name":1241,"slug":1242,"type":15},"2026-07-14T05:25:59.97109",{"slug":1369,"name":1369,"fn":1370,"description":1371,"org":1372,"tags":1373,"stars":1354,"repoUrl":1355,"updatedAt":1379},"mcore-cicd","manage CI\u002FCD pipelines for Megatron-LM","CI\u002FCD reference for Megatron-LM. Covers CI pipeline structure, PR scope labels, triggering internal GitLab CI (which force-pushes the current branch to a pull-request\u002FBRANCH ref — always dry-run and verify the destination first; never run against shared or protected branches), and CI failure investigation.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1374,1375,1376],{"name":1364,"slug":1365,"type":15},{"name":1241,"slug":1242,"type":15},{"name":1377,"slug":1378,"type":15},"GitHub","github","2026-07-27T06:06:12.278222",{"slug":1381,"name":1381,"fn":1382,"description":1383,"org":1384,"tags":1385,"stars":1354,"repoUrl":1355,"updatedAt":1393},"mcore-create-issue","investigate CI failures and create issues","Investigate a failing GitHub Actions run or job and create a GitHub issue for the failure.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1386,1389,1390],{"name":1387,"slug":1388,"type":15},"Debugging","debugging",{"name":1377,"slug":1378,"type":15},{"name":1391,"slug":1392,"type":15},"Triage","triage","2026-07-14T05:25:57.442089",{"slug":1395,"name":1395,"fn":1396,"description":1397,"org":1398,"tags":1399,"stars":1354,"repoUrl":1355,"updatedAt":1406},"mcore-linting-and-formatting","lint and format Megatron-LM code","Linting and formatting for Megatron-LM. Covers running autoformat.sh, tools (ruff, black, isort, pylint, mypy), and code style rules.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1400,1403],{"name":1401,"slug":1402,"type":15},"Best Practices","best-practices",{"name":1404,"slug":1405,"type":15},"Code Analysis","code-analysis","2026-07-14T05:25:56.18433",{"slug":1408,"name":1408,"fn":1409,"description":1410,"org":1411,"tags":1412,"stars":1354,"repoUrl":1355,"updatedAt":1420},"mcore-migrate-gpt-to-hybrid","migrate Megatron-LM models to HybridModel","Migration guide for moving Megatron Core GPTModel checkpoints, model providers, training commands, and layer mappings to HybridModel.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1413,1416,1419],{"name":1414,"slug":1415,"type":15},"Machine Learning","machine-learning",{"name":1417,"slug":1418,"type":15},"Migration","migration",{"name":9,"slug":8,"type":15},"2026-07-17T06:07:11.777011",{"slug":1422,"name":1422,"fn":1423,"description":1424,"org":1425,"tags":1426,"stars":1354,"repoUrl":1355,"updatedAt":1431},"mcore-onboard-gb200-1node-tests","onboard functional tests for GB200","Onboard 1-node GitHub MR functional tests for GB200 from existing mr-scoped 2-node tests.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1427,1430],{"name":1428,"slug":1429,"type":15},"QA","qa",{"name":1271,"slug":1272,"type":15},"2026-07-14T05:25:53.673039",{"slug":1433,"name":1433,"fn":1434,"description":1435,"org":1436,"tags":1437,"stars":1354,"repoUrl":1355,"updatedAt":1440},"mcore-run-on-slurm","launch distributed training jobs on SLURM","How to launch distributed Megatron-LM training jobs on a SLURM cluster. Covers a minimal sbatch skeleton, environment-variable setup for torch.distributed.run, CUDA_DEVICE_MAX_CONNECTIONS rules across hardware and parallelism modes, container conventions, monitoring, and per-rank failure diagnosis.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1438,1439],{"name":1241,"slug":1242,"type":15},{"name":1244,"slug":1245,"type":15},"2026-07-14T05:25:49.362534",{"slug":1442,"name":1442,"fn":1443,"description":1444,"org":1445,"tags":1446,"stars":1354,"repoUrl":1355,"updatedAt":1454},"mcore-split-pr","split pull requests to reduce review load","Split a PR into multiple PRs to reduce the number of required CODEOWNERS reviewer groups.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1447,1450,1451],{"name":1448,"slug":1449,"type":15},"Code Review","code-review",{"name":1377,"slug":1378,"type":15},{"name":1452,"slug":1453,"type":15},"Pull Requests","pull-requests","2026-07-14T05:26:01.226578",{"slug":1456,"name":1456,"fn":1457,"description":1458,"org":1459,"tags":1460,"stars":1354,"repoUrl":1355,"updatedAt":1463},"mcore-testing","run and manage Megatron-LM tests","Test system for Megatron-LM. Covers test layout, recipe YAML structure, adding and running unit and functional tests, golden values, marker filters, and CI parity.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1461,1462],{"name":1428,"slug":1429,"type":15},{"name":1271,"slug":1272,"type":15},"2026-07-14T05:25:54.928983",{"slug":1465,"name":1465,"fn":1466,"description":1467,"org":1468,"tags":1469,"stars":1354,"repoUrl":1355,"updatedAt":1472},"nightly-sync","manage nightly main-to-dev sync workflows","Domain knowledge for the nightly main-to-dev sync workflow. Covers merge strategy, CI architecture, failure investigation, and known issues.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1470,1471],{"name":1281,"slug":1282,"type":15},{"name":1364,"slug":1365,"type":15},"2026-07-30T05:29:03.275638",496]