[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill-nvidia-jetson-customize-pinmux":3,"mdc-cblead-key":34,"related-repo-nvidia-jetson-customize-pinmux":1684,"related-org-nvidia-jetson-customize-pinmux":1790},{"slug":4,"name":4,"fn":5,"description":6,"org":7,"tags":11,"stars":23,"repoUrl":24,"updatedAt":25,"license":26,"forks":27,"topics":28,"repo":29,"sourceUrl":32,"mdContent":33},"jetson-customize-pinmux","configure Jetson pinmux settings","Per-pin SFIO \u002F direction \u002F initial-state configurator for a Jetson Orin or Thor custom carrier from the pinmux XLSM. Do NOT use for kernel-DT overlay or ODMDATA edits.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},"nvidia","NVIDIA","https:\u002F\u002Fpexgzepcugksgbtrxkhf.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Forg-logos\u002Fnvidia.png",[12,16,19,20],{"name":13,"slug":14,"type":15},"Configuration","configuration","tag",{"name":17,"slug":18,"type":15},"Hardware","hardware",{"name":9,"slug":8,"type":15},{"name":21,"slug":22,"type":15},"Engineering","engineering",2473,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills","2026-07-14T05:28:04.343351","Apache-2.0",281,[],{"repoUrl":24,"stars":23,"forks":27,"topics":30,"description":31},[],"AI agent skills published by NVIDIA","https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills\u002Ftree\u002FHEAD\u002Fskills\u002Fjetson-customize-pinmux","---\nname: jetson-customize-pinmux\ndescription: >-\n  Per-pin SFIO \u002F direction \u002F initial-state configurator for a Jetson\n  Orin or Thor custom carrier from the pinmux XLSM. Do NOT use for\n  kernel-DT overlay or ODMDATA edits.\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - bsp\n    - phase-2\n    - io\n    - pinmux\n  domain: meta\n---\n\n# Customize pinmux (per-pin SFIO \u002F direction \u002F state)\n\n## Overview\n\nThe Tegra pinmux spreadsheet (`.xlsm`) is the ground truth for every\nCVM ball: SoC pin name, supported SFIOs, customer-selected function,\ndirection, and initial state. This skill parses that XLSM, runs a\nper-pin Q1–Q6 interactive loop, and emits the three BCT DTSIs\n(`pinmux`, `gpio`, `padvoltage`) in one shot into the overlay tracker\nat `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F`.\n\nUnlike sibling skills `jetson-customize-uphy` \u002F `jetson-customize-pcie` \u002F\n`jetson-customize-camera`, **pinmux has no kernel-DT overlay surface and no\nODMDATA edit**. The XLSM is the source of truth; the three emitted\nDTSIs land at flash time via the carrier conf's\n`PINMUX_CONFIG=` \u002F `GPIOINT_CONFIG=` \u002F `PMC_CONFIG=` references (which\n`\u002Fjetson-derive-carrier` set up).\n\n**Pad classification (silicon-fixed):** only `BD*` and `BI*` pads have\nconfigurable pull \u002F drive \u002F open-drain attributes. `LP5XA_*`,\n`UPHYDS_*`, `DP_SINGLE_*`, `BDMIPI16X_*`, `BDUSB2_*`, `OSCI27_*` are\nfixed-function and **skip Q4–Q6** (`configurable: no`).\n\nThe bundled `scripts\u002Fmodify_pinmux.py` is the workhorse: it parses\nthe XLSM via `openpyxl>=3.1`, builds the per-carrier pinmap JSON,\ncaptures pin edits into a session shim, and (on `generate`) writes\nthe three DTSIs.\n\n## When to invoke\n\n- The user says \"configure pin\", \"set SFIO\", \"edit pinmux DTSI\",\n  \"set pin direction\", \"set initial state\", or asks to repurpose a\n  CVM ball (e.g. flip a pin between GPIO and a peripheral function).\n- A sibling skill (`jetson-customize-camera`, `jetson-customize-pcie`,\n  `jetson-customize-usb`, `jetson-customize-mgbe`) reports an HSIO pin mismatch\n  via `pin_verifier.py` and the user wants to fix it.\n- The user pre-derived a custom carrier with `\u002Fjetson-derive-carrier`\n  and now wants to author the pinmux from a freshly-edited `.xlsm`.\n\n**Prerequisites:**\n\n- Active profile selected (`target-platform\u002Factive_target.yml` →\n  `\u003Cprofile>.yaml` with `reference_devkit:` AND `custom_carrier:`).\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` exists as a git repo\n  (`\u002Fjetson-init-source`).\n- `\u002Fjetson-derive-carrier` has run — the three pinmux-side BCT DTSIs\n  (`PINMUX_CONFIG`, `GPIOINT_CONFIG`, `PMC_CONFIG` references in the\n  carrier conf) exist in the overlay tracker.\n- A pinmux `.xlsm` is registered in the active profile at\n  `documents.custom_carrier_pinmux_xls` (preferred when custom-carrier-\n  specific) or `documents.ref_devkit_pinmux_xls` (fallback). The\n  bundled `modify_pinmux.py` requires `openpyxl>=3.1`.\n\n## Procedure\n\nSee [`references\u002Fprocedure.md`](references\u002Fprocedure.md) for the full\nstep-by-step procedure (Steps 1–8). Summary:\n\n1. **Resolve active target + XLSM.** Validate active profile,\n   `custom_carrier:`, overlay-tracker prerequisites; resolve the\n   pinmux `.xlsm` path from\n   `documents.custom_carrier_pinmux_xls` →\n   `documents.ref_devkit_pinmux_xls` → single XLSM under\n   `documents.root_path` → user prompt.\n2. **Probe.** Run `modify_pinmux.py probe` to parse the XLSM into the\n   per-skill scratch `\u003CKB>\u002Fpinmap\u002F\u003Ccustom-carrier>.json` plus\n   `session.json` shim.\n3. **Lookup.** Resolve a free-form user query (CVM ball, Verilog\n   name, signal, DT pin) via `modify_pinmux.py lookup`; surface\n   supported SFIO list, defaults, and `configurable: yes\u002Fno`.\n4. **Set-pin (HARD GATE — Q1–Q6 via `AskUserQuestion`).** Q1–Q3\n   (`sfio` \u002F `direction` \u002F `initial_state`) always asked; Q4–Q6\n   (`pull` \u002F `drive_type` \u002F `open_drain`) only when\n   `configurable: yes`. `tristate` and `e_input` are derived from\n   `direction`, never asked.\n5. **Generate.** `modify_pinmux.py generate --out-dir\n   \u003Csource.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F` (root, **not**\n   `bootloader\u002Fgeneric\u002FBCT\u002F` — derive-carrier `.dts` forks live there,\n   do not colocate). Emits:\n   `tegra\u003Csoc>-mb1-bct-{pinmux,gpio,padvoltage}-\u003Ccarrier-key>.dtsi`.\n   **`\u003Ccarrier-key>` comes from the carrier conf's `PINMUX_CONFIG=`\n   reference, NOT the kebab-cased carrier name.**\n6. **Commit (single batched commit per workflow rule).** All three\n   DTSIs are one logical edit → one customization commit. Run the\n   commit-preview gate before each commit.\n7. **Run-state sidecar + session shim.** Write the user-facing\n   `\u003Cprofile-stem>.jetson-customize-pinmux.json` sidecar and the\n   transient `session.json` shim under\n   `\u003Cworkspace>\u002Ftarget-platform\u002F`.\n8. **Summary.** Emit the standard one-line + table summary.\n\n## Gotchas\n\n- **No kernel-DT overlay; no `OVERLAY_DTB_FILE` edit; no\n  `render_conf.py` hand-off.** This skill ends at the three BCT\n  DTSIs — the carrier conf already references them via\n  `PINMUX_CONFIG=` \u002F `GPIOINT_CONFIG=` \u002F `PMC_CONFIG=` (set up by\n  `\u002Fjetson-derive-carrier`).\n- **Re-point the `.dts` wrapper's `#include` after `generate`.**\n  `\u002Fjetson-derive-carrier` forks the `.dts` wrappers at\n  `bootloader\u002Fgeneric\u002FBCT\u002F`, but their `#include` lines may still\n  pull the upstream devkit `.dtsi` (e.g.\n  `…-p3834-xxxx-p4071-0000.dtsi`). After `generate` writes the new\n  `\u003CCARRIER_KEY>.dtsi` to `bootloader\u002F` root, edit each wrapper's\n  `#include` to the new filename — by **bare basename**\n  (`#include \"tegra\u003Csoc>-mb1-bct-pinmux-\u003CCARRIER_KEY>.dtsi\"`), not\n  `..\u002F..\u002F…` filesystem-relative. The BCT build's `cpp -I bootloader\u002F`\n  resolves bare basenames; that's the convention every other BCT\n  include in the tree follows. Roll the wrapper edits into the same\n  customization commit as the three DTSIs. See `references\u002Fprocedure.md`\n  Step 5 (\"Sanity-check the carrier `.dts` wrapper\").\n- **Q4–Q6 gated on `configurable: yes`.** Asking pull \u002F drive_type \u002F\n  open_drain on a fixed-function pad (`LP5XA_*`, `UPHYDS_*`,\n  `BDMIPI16X_*`, etc.) is silently dropped by the script and confuses\n  the user. `lookup` prints `configurable: yes\u002Fno` — always check it\n  before prompting Q4–Q6.\n- **`tristate` and `e_input` are derived, never asked.** `unused` →\n  tristate=ENABLE; `input` \u002F `bidirectional` → enable-input=ENABLE.\n  Exposing them as separate prompts produces inconsistent DTSIs.\n- **`sfio=gpio` requires a parseable `gpio=GPIOn_PD.NN` entry in the\n  pinmap row's `sfio` list.** Pins without one are GPIO-incapable\n  silicon; `set-pin` rejects the call. Surface the rejection — don't\n  silently fall back to a non-GPIO SFIO.\n- **Marker idempotency.** Every per-pin edit carries\n  `\u002F\u002F custom-bsp: pinmux` on the closing brace; gpio default-state\n  entries carry the same marker as a trailing comment. Re-running\n  `generate` must detect and update — never duplicate.\n- **`modify_pinmux.py` is unchanged from the original framework** —\n  it reads its own `session.json` shim under `--kb-dir`. The shim\n  is regenerated each run from the active profile + the user-facing\n  sidecar. Do not hand-edit the shim; it's transient.\n- **Multiple pinmux DTSI variants per Thor module SKU.** Some carrier\n  pins live in a different DTSI variant than the one the carrier\n  conf references. `modify_pinmux.py commit` (legacy patch-in-place\n  flow) tolerates missing per-pin blocks via\n  `pinmux.warnings[]` rather than failing. Surface the warning;\n  point at the alternate DTSI variant.\n- **Don't touch the upstream BSP at `\u003Cbsp_image.root_path>`.** All\n  edits land in `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F` under\n  the pristine + customization commit pattern.\n\n## Available Scripts\n\n| Script | Purpose | Arguments |\n|---|---|---|\n| `scripts\u002Fmodify_pinmux.py` | XLSM parser + per-pin DTSI generator. Invoked via `run_script()` from Steps 3-6 with the subcommand of the current phase. | `probe \\| lookup \\| set-pin \\| apply \\| generate \\| commit [...]` (see `--help`) |\n| `scripts\u002Fgenerate_dtsi.py` | Renders pinmux\u002FGPIO\u002Fpadvoltage DTSI fragments from the bundled session state. Called by `modify_pinmux.py generate`. | `--session \u003Cpath> --out-dir \u003Cdir>` |\n\nInvoke from the skill body as a subprocess via `run_script()`:\n\n```bash\n# run_script: probe the carrier pinmux XLSM and write a session state\nscripts\u002Fmodify_pinmux.py probe --xlsm carrier.xlsm --session .pinmux-session.json\n\n# run_script: render DTSI fragments from the final session state\nscripts\u002Fmodify_pinmux.py generate --session .pinmux-session.json --out-dir bsp_sources\u002Fpinmux\u002F\n```\n\n## References\n- [`references\u002Fprocedure.md`](references\u002Fprocedure.md) — full Step 1–8\n  procedure prose.\n- [`questions.json`](questions.json) — Q1–Q6 prompt schema consumed\n  by Step 4.\n- [`..\u002F..\u002Freferences\u002Fplatform_template.yaml`](..\u002F..\u002Freferences\u002Fplatform_template.yaml) — `documents:` block (`ref_devkit_pinmux_xls`, `custom_carrier_pinmux_xls`).\n- [`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md`](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants) — overlay edit protocol (single-commit per DTSI fork).\n- [`..\u002Fjetson-derive-carrier\u002FSKILL.md`](..\u002Fjetson-derive-carrier\u002FSKILL.md) — must run first; produces the pinmux \u002F gpio \u002F padvoltage DTSI forks this skill edits, and rewrites the carrier conf's `PINMUX_CONFIG=` \u002F `GPIOINT_CONFIG=` \u002F `PMC_CONFIG=` lines to point at them.\n- [`..\u002Fjetson-init-source\u002FSKILL.md`](..\u002Fjetson-init-source\u002FSKILL.md) — produces the overlay tracker this skill commits into.\n- [`..\u002Fjetson-link-docs\u002FSKILL.md`](..\u002Fjetson-link-docs\u002FSKILL.md) — author the profile's `documents:` block, including the pinmux XLSM bindings.\n",{"data":35,"body":46},{"name":4,"description":6,"version":36,"license":26,"metadata":37},"0.0.1",{"data-classification":38,"author":39,"tags":40,"domain":45},"public","Jetson Team",[41,42,43,44],"bsp","phase-2","io","pinmux","meta",{"type":47,"children":48},"root",[49,58,65,110,176,261,290,296,364,372,503,509,526,842,848,1287,1293,1402,1414,1523,1529,1678],{"type":50,"tag":51,"props":52,"children":54},"element","h1",{"id":53},"customize-pinmux-per-pin-sfio-direction-state",[55],{"type":56,"value":57},"text","Customize pinmux (per-pin SFIO \u002F direction \u002F state)",{"type":50,"tag":59,"props":60,"children":62},"h2",{"id":61},"overview",[63],{"type":56,"value":64},"Overview",{"type":50,"tag":66,"props":67,"children":68},"p",{},[69,71,78,80,85,87,93,94,100,102,108],{"type":56,"value":70},"The Tegra pinmux spreadsheet (",{"type":50,"tag":72,"props":73,"children":75},"code",{"className":74},[],[76],{"type":56,"value":77},".xlsm",{"type":56,"value":79},") is the ground truth for every\nCVM ball: SoC pin name, supported SFIOs, customer-selected function,\ndirection, and initial state. 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Covers the two pin sites (GitHub CI in `docker\u002F.ngc_version.dev` and GitLab CI in `.gitlab\u002Fstages\u002F01.build.yml`), the post-bump CI loop (re-run functional tests, refresh golden values, mark broken tests), and the gotchas that bit PRs",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1832,1835],{"name":1833,"slug":1834,"type":15},"CI\u002FCD","ci-cd",{"name":1710,"slug":1711,"type":15},"2026-07-14T05:25:59.97109",{"slug":1838,"name":1838,"fn":1839,"description":1840,"org":1841,"tags":1842,"stars":1823,"repoUrl":1824,"updatedAt":1848},"mcore-cicd","manage CI\u002FCD pipelines for Megatron-LM","CI\u002FCD reference for Megatron-LM. Covers CI pipeline structure, PR scope labels, triggering internal GitLab CI (which force-pushes the current branch to a pull-request\u002FBRANCH ref — always dry-run and verify the destination first; never run against shared or protected branches), and CI failure investigation.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1843,1844,1845],{"name":1833,"slug":1834,"type":15},{"name":1710,"slug":1711,"type":15},{"name":1846,"slug":1847,"type":15},"GitHub","github","2026-07-27T06:06:12.278222",{"slug":1850,"name":1850,"fn":1851,"description":1852,"org":1853,"tags":1854,"stars":1823,"repoUrl":1824,"updatedAt":1862},"mcore-create-issue","investigate CI failures and create issues","Investigate a failing GitHub Actions run or job and create a GitHub issue for the failure.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1855,1858,1859],{"name":1856,"slug":1857,"type":15},"Debugging","debugging",{"name":1846,"slug":1847,"type":15},{"name":1860,"slug":1861,"type":15},"Triage","triage","2026-07-14T05:25:57.442089",{"slug":1864,"name":1864,"fn":1865,"description":1866,"org":1867,"tags":1868,"stars":1823,"repoUrl":1824,"updatedAt":1875},"mcore-linting-and-formatting","lint and format Megatron-LM code","Linting and formatting for Megatron-LM. Covers running autoformat.sh, tools (ruff, black, isort, pylint, mypy), and code style rules.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1869,1872],{"name":1870,"slug":1871,"type":15},"Best Practices","best-practices",{"name":1873,"slug":1874,"type":15},"Code Analysis","code-analysis","2026-07-14T05:25:56.18433",{"slug":1877,"name":1877,"fn":1878,"description":1879,"org":1880,"tags":1881,"stars":1823,"repoUrl":1824,"updatedAt":1889},"mcore-migrate-gpt-to-hybrid","migrate Megatron-LM models to HybridModel","Migration guide for moving Megatron Core GPTModel checkpoints, model providers, training commands, and layer mappings to HybridModel.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1882,1885,1888],{"name":1883,"slug":1884,"type":15},"Machine Learning","machine-learning",{"name":1886,"slug":1887,"type":15},"Migration","migration",{"name":9,"slug":8,"type":15},"2026-07-17T06:07:11.777011",{"slug":1891,"name":1891,"fn":1892,"description":1893,"org":1894,"tags":1895,"stars":1823,"repoUrl":1824,"updatedAt":1900},"mcore-onboard-gb200-1node-tests","onboard functional tests for GB200","Onboard 1-node GitHub MR functional tests for GB200 from existing mr-scoped 2-node tests.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1896,1899],{"name":1897,"slug":1898,"type":15},"QA","qa",{"name":1740,"slug":1741,"type":15},"2026-07-14T05:25:53.673039",{"slug":1902,"name":1902,"fn":1903,"description":1904,"org":1905,"tags":1906,"stars":1823,"repoUrl":1824,"updatedAt":1909},"mcore-run-on-slurm","launch distributed training jobs on SLURM","How to launch distributed Megatron-LM training jobs on a SLURM cluster. Covers a minimal sbatch skeleton, environment-variable setup for torch.distributed.run, CUDA_DEVICE_MAX_CONNECTIONS rules across hardware and parallelism modes, container conventions, monitoring, and per-rank failure diagnosis.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1907,1908],{"name":1710,"slug":1711,"type":15},{"name":1713,"slug":1714,"type":15},"2026-07-14T05:25:49.362534",{"slug":1911,"name":1911,"fn":1912,"description":1913,"org":1914,"tags":1915,"stars":1823,"repoUrl":1824,"updatedAt":1923},"mcore-split-pr","split pull requests to reduce review load","Split a PR into multiple PRs to reduce the number of required CODEOWNERS reviewer groups.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1916,1919,1920],{"name":1917,"slug":1918,"type":15},"Code Review","code-review",{"name":1846,"slug":1847,"type":15},{"name":1921,"slug":1922,"type":15},"Pull Requests","pull-requests","2026-07-14T05:26:01.226578",{"slug":1925,"name":1925,"fn":1926,"description":1927,"org":1928,"tags":1929,"stars":1823,"repoUrl":1824,"updatedAt":1932},"mcore-testing","run and manage Megatron-LM tests","Test system for Megatron-LM. Covers test layout, recipe YAML structure, adding and running unit and functional tests, golden values, marker filters, and CI parity.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1930,1931],{"name":1897,"slug":1898,"type":15},{"name":1740,"slug":1741,"type":15},"2026-07-14T05:25:54.928983",{"slug":1934,"name":1934,"fn":1935,"description":1936,"org":1937,"tags":1938,"stars":1823,"repoUrl":1824,"updatedAt":1941},"nightly-sync","manage nightly main-to-dev sync workflows","Domain knowledge for the nightly main-to-dev sync workflow. Covers merge strategy, CI architecture, failure investigation, and known issues.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1939,1940],{"name":1750,"slug":1751,"type":15},{"name":1833,"slug":1834,"type":15},"2026-07-30T05:29:03.275638",496]