[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill-nvidia-jetson-customize-pcie":3,"mdc--iq478q-key":31,"related-repo-nvidia-jetson-customize-pcie":1394,"related-org-nvidia-jetson-customize-pcie":1500},{"slug":4,"name":4,"fn":5,"description":6,"org":7,"tags":11,"stars":20,"repoUrl":21,"updatedAt":22,"license":23,"forks":24,"topics":25,"repo":26,"sourceUrl":29,"mdContent":30},"jetson-customize-pcie","customize Jetson PCIe controller settings","Per-controller PCIe enable \u002F disable \u002F lanes \u002F link-speed for a Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay. Do NOT use for UPHY lane allocation or endpoint-mode bring-up.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},"nvidia","NVIDIA","https:\u002F\u002Fpexgzepcugksgbtrxkhf.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Forg-logos\u002Fnvidia.png",[12,16,17],{"name":13,"slug":14,"type":15},"Hardware","hardware","tag",{"name":9,"slug":8,"type":15},{"name":18,"slug":19,"type":15},"Engineering","engineering",2473,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills","2026-07-14T05:28:27.123403","Apache-2.0",281,[],{"repoUrl":21,"stars":20,"forks":24,"topics":27,"description":28},[],"AI agent skills published by NVIDIA","https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills\u002Ftree\u002FHEAD\u002Fskills\u002Fjetson-customize-pcie","---\nname: jetson-customize-pcie\ndescription: >-\n  Per-controller PCIe enable \u002F disable \u002F lanes \u002F link-speed for a\n  Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay.\n  Do NOT use for UPHY lane allocation or endpoint-mode bring-up.\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - bsp\n    - phase-2\n    - io\n    - pcie\n  domain: meta\n---\n\n# Customize PCIe (per-controller status \u002F lanes \u002F speed)\n\n## Overview\n\nPCIe on Tegra264 (Thor, `pcie@C0..C5`) and Tegra234 (Orin,\n`pcie@C0..C10`) is split across multiple controllers that share the\nUPHY lane pool with USB3 \u002F MGBE \u002F UFS. Each controller's runtime\nbehavior is determined by **two surfaces, both required**:\n\n| Surface | Target | Authoritative for |\n|---|---|---|\n| ODMDATA `pcie@N_status=…` (+ `pcie@N_max-link-speed`, `pcie@N_pcie-mode`, `pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`) | `\u002Fpcie\u002Fpcie@N` in BPMP DTB | UPHY lane power, refclk gating, controller-side power rails |\n| Kernel-DT overlay on `&pcieN` | `\u002Fbus@0\u002Fpcie@\u003Caddr>` in kernel DTB | Kernel probe, lane width, link speed, RC\u002FEP mode |\n\nSkipping the kernel overlay on a disable lets the kernel probe a\npowered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token\non a disable leaves BPMP holding the PHY hot.\n\n**Agentic, not table-driven** — no controller table, no\n`questions.json`. Every controller, lane width, schematic-routed\nreceptacle, and authoritative DT node address is discovered at runtime\nfrom the docs + DTB + carrier pinmap.\n\nThe output is a **kernel-DT overlay commit only**. Per-controller\n`fragment@N` blocks are appended to the composite custom overlay\n`.dts` per\n[`..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md)\nand committed to the `bsp_sources\u002F` hardware repo.\n`\u002Fjetson-build-source` compiles the composite to `.dtbo` and owns its\nMakefile + flash-conf registration.\n\n**This skill MUST NOT edit `ODMDATA=\"...\"`.** All ODMDATA tokens\n(`pcie@N_status=…`, `pcie@N_max-link-speed`, `pcie@N_pcie-mode`,\n`pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`, plus the\n`uphyX-config-N` surface tokens and `UPHY_CONFIG=\"\"` clear) are\nemitted by `\u002Fjetson-customize-uphy` in a single atomic commit on the\ncarrier flash-conf fork. The allocation table this skill consumes\nfrom the UPHY sidecar already tells the operator which controllers\nare `okay` \u002F `disabled` \u002F per-lane sized; this skill only translates\nthat table into kernel-DT overlay fragments and verifies that the\noverlay agrees with the ODMDATA already committed by `customize-uphy`\n(consistency check in Step 8 — disagreement is reported, not silently\nfixed).\n\n## When to invoke\n\n- The user says \"configure PCIe\", \"enable PCIe controller\", \"set PCIe\n  num-lanes\", \"change PCIe link speed\", or asks to flip a\n  `pcie@N_status` token.\n- A specific PCIe slot or M.2 receptacle doesn't enumerate after\n  flash, OR the link trains at the wrong width \u002F speed.\n- `jetson-customize-uphy` ran and re-allocated lanes across PCIe controllers\n  (e.g. switched from `uphy0-config-7` to `uphy0-config-6` enabling\n  PCIe C3); the per-controller side now needs to be brought up.\n- `jetson-customize-mgbe` reports the QSFP path is wired but the kernel\n  doesn't probe its PCIe-side companion (rare; XFI configurations).\n\n**Prerequisites:**\n\n- Active profile with `reference_devkit:` + `custom_carrier:` blocks.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` exists\n  (`\u002Fjetson-init-source`).\n- `\u002Fjetson-derive-carrier` has run — carrier flash-conf fork is in\n  the overlay tracker.\n- `\u002Fjetson-customize-uphy` has run — its JSON sidecar at\n  `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-uphy.json`\n  drives the per-controller `enable` decision.\n- Source-of-truth docs registered or supplied at prompt: Adaptation\n  Guide, Module Design Guide, SoC TRM.\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** Refuse the run\n  if either is missing — routing on a custom carrier cannot be guessed.\n  Reference-devkit-only profiles skip this check.\n- `dtc` on PATH.\n\n## Procedure (summary)\n\nFull step-by-step walkthrough lives in\n[`references\u002Fprocedure.md`](references\u002Fprocedure.md). High-level flow:\n\n1. Resolve active target + open source-of-truth documents (incl.\n   `\u003Ccarrier-pinmap>`, `\u003Cref-dtb>`, `\u003Cuphy-state>`). Refuse if\n   `\u003Cuphy-state>` is missing.\n2. Diff PCIe topology — devkit vs custom carrier — by decompiling\n   `\u003Cref-dtb>` and grepping the schematic for `PEX\u003CN>_*` net labels.\n3. `AskUserQuestion` (multiSelect) — which controllers to customize.\n4. Per-controller verification: pinmap + schematic + `pin_verifier.py`\n   for `PE\u003CN>_CLKREQ_L`, `PE\u003CN>_RST_L`, optional `PE\u003CN>_WAKE_L`.\n5. Auto-derive per-controller plan (`enable` from `\u003Cuphy-state>`,\n   `lanes` \u002F `speed` from Adaptation Guide, `mode` hard-pinned to\n   `\"rc\"`) → mandatory confirm-or-customize gate.\n6. Append per-controller `fragment@N` blocks (marker\n   `\u002F* custom-bsp: pcie:pcie@\u003Caddr> *\u002F`) to the composite custom\n   overlay `.dts` in `bsp_sources\u002F`. Pre-flight `dtc` + `fdtoverlay`.\n   Commit via the workflow's preview gate.\n   **Do not edit `ODMDATA`** — `\u002Fjetson-customize-uphy` already emitted\n   `pcie@N_status=…`, `pcie@N_max-link-speed`, `pcie@N_pcie-mode`,\n   `pcie@N_clk-scheme`, and `pcie-cN-endpoint-enable` in its single\n   atomic ODMDATA commit. This skill only translates the per-controller\n   plan into kernel-DT overlay fragments.\n7. (Step folded into Step 6 — overlay-only emission.)\n8. Cross-check ODMDATA vs overlay consistency. On a contradictory\n   row, **stop and ask the user how to recover the two commits.\n   Never run `git reset --hard` autonomously.**\n9. Write run-state JSON sidecar at\n   `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-pcie.json`\n   + summary, then drive the downstream next-step chain via sequential\n   `AskUserQuestion` prompts per `references\u002Fprocedure.md` Step 9.\n   Never substitute a printed \"Next step: …\" line for the prompts.\n\n## Limitations\n\n- **Mode hard-pinned to RC.** Endpoint mode is only emitted when the\n  operator passes `mode_override=\"ep\"` in Step 5c.\n- **`enable` is derived, not asked.** UPHY-allocated controllers are\n  mandatorily `okay`; non-allocated are mandatorily `disabled`.\n- **No upstream BSP edits.** Output lands in `Linux_for_Tegra\u002F` +\n  `bsp_sources\u002F` only.\n- **Pre-flight overlay merge is a sanity check**, not the production\n  build. `\u002Fjetson-build-source` is authoritative.\n- **Flash-conf overlay registration is out of scope.** Owned by\n  `\u002Fjetson-build-source` Step 5.0a.\n\n## Troubleshooting\n\n- **`\u003Cuphy-state>` missing** → run `\u002Fjetson-customize-uphy` first.\n- **Slot doesn't enumerate after flash** → check `dmesg | grep pcie`;\n  re-verify ODMDATA `pcie@\u003CN>_status=okay` and the overlay fragment\n  agree (Step 8 table in\n  [`references\u002Fprocedure.md`](references\u002Fprocedure.md)).\n- **Link trains at wrong width** → confirm UPHY config in\n  `\u003Cuphy-state>` allocates the expected lane count; the kernel\n  fragment's `num-lanes` must match.\n- **`compatible` mismatch** → fix the composite root, not the\n  fragment. UEFI plugin-manager silently skips on mismatch.\n- **Contradictory ODMDATA-vs-overlay row** → ask the user; do not\n  auto-`git reset --hard`. See gotchas.\n- **Common pitfalls** — see\n  [`references\u002Fgotchas.md`](references\u002Fgotchas.md) (RC pinning, node-\n  address sourcing, stock-disabled controllers, intra-file handoff\n  with `jetson-customize-uphy`).\n\n## References\n\n- [`references\u002Fprocedure.md`](references\u002Fprocedure.md) — full nine-\n  step procedure (topology diff, plan derivation, overlay append,\n  ODMDATA cross-check, sidecar).\n- [`references\u002Fgotchas.md`](references\u002Fgotchas.md) — failure modes\n  + invariants (RC pinning, address sourcing, BPMP handoff).\n- [`..\u002F..\u002Fscripts\u002Fpin_verifier.py`](..\u002F..\u002Fscripts\u002Fpin_verifier.py)\n  — shared HSIO pin verifier (Step 4).\n- [`..\u002F..\u002Freferences\u002Fplatform_template.yaml`](..\u002F..\u002Freferences\u002Fplatform_template.yaml)\n  — `documents:` block consumed by Step 1.\n- [`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md`](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants)\n  — overlay edit protocol + commit message preview gate.\n- [`..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md)\n  — composite overlay filename \u002F skeleton \u002F append protocol.\n- [`..\u002Fjetson-customize-uphy\u002FSKILL.md`](..\u002Fjetson-customize-uphy\u002FSKILL.md)\n  — sibling skill that owns UPHY lane allocation; its sidecar drives\n  the per-controller `enable` decision.\n- [`..\u002Fjetson-customize-pinmux\u002FSKILL.md`](..\u002Fjetson-customize-pinmux\u002FSKILL.md)\n  — sibling skill invoked by Step 4 (with operator confirmation) to\n  fix HSIO pin SFIO mismatches.\n- [`..\u002Fjetson-customize-mgbe\u002FSKILL.md`](..\u002Fjetson-customize-mgbe\u002FSKILL.md)\n  — sibling for MGBE controllers; shares the two-surface (ODMDATA\n  + overlay) pattern.\n- [`..\u002Fjetson-derive-carrier\u002FSKILL.md`](..\u002Fjetson-derive-carrier\u002FSKILL.md)\n  — must run first; produces the carrier flash-conf fork edited in\n  Step 6.\n- [`..\u002Fjetson-init-source\u002FSKILL.md`](..\u002Fjetson-init-source\u002FSKILL.md)\n  — produces the overlay tracker + bsp_sources repo this skill\n  commits into.\n",{"data":32,"body":43},{"name":4,"description":6,"version":33,"license":23,"metadata":34},"0.0.1",{"data-classification":35,"author":36,"tags":37,"domain":42},"public","Jetson Team",[38,39,40,41],"bsp","phase-2","io","pcie","meta",{"type":44,"children":45},"root",[46,55,62,93,218,223,241,305,403,409,470,478,607,613,629,938,944,1052,1058,1203,1209],{"type":47,"tag":48,"props":49,"children":51},"element","h1",{"id":50},"customize-pcie-per-controller-status-lanes-speed",[52],{"type":53,"value":54},"text","Customize PCIe (per-controller status \u002F lanes \u002F speed)",{"type":47,"tag":56,"props":57,"children":59},"h2",{"id":58},"overview",[60],{"type":53,"value":61},"Overview",{"type":47,"tag":63,"props":64,"children":65},"p",{},[66,68,75,77,83,85,91],{"type":53,"value":67},"PCIe on Tegra264 (Thor, ",{"type":47,"tag":69,"props":70,"children":72},"code",{"className":71},[],[73],{"type":53,"value":74},"pcie@C0..C5",{"type":53,"value":76},") and Tegra234 (Orin,\n",{"type":47,"tag":69,"props":78,"children":80},{"className":79},[],[81],{"type":53,"value":82},"pcie@C0..C10",{"type":53,"value":84},") is split across multiple controllers that share the\nUPHY lane pool with USB3 \u002F MGBE \u002F UFS. Each controller's runtime\nbehavior is determined by ",{"type":47,"tag":86,"props":87,"children":88},"strong",{},[89],{"type":53,"value":90},"two surfaces, both required",{"type":53,"value":92},":",{"type":47,"tag":94,"props":95,"children":96},"table",{},[97,121],{"type":47,"tag":98,"props":99,"children":100},"thead",{},[101],{"type":47,"tag":102,"props":103,"children":104},"tr",{},[105,111,116],{"type":47,"tag":106,"props":107,"children":108},"th",{},[109],{"type":53,"value":110},"Surface",{"type":47,"tag":106,"props":112,"children":113},{},[114],{"type":53,"value":115},"Target",{"type":47,"tag":106,"props":117,"children":118},{},[119],{"type":53,"value":120},"Authoritative for",{"type":47,"tag":122,"props":123,"children":124},"tbody",{},[125,188],{"type":47,"tag":102,"props":126,"children":127},{},[128,172,183],{"type":47,"tag":129,"props":130,"children":131},"td",{},[132,134,140,142,148,150,156,157,163,164,170],{"type":53,"value":133},"ODMDATA ",{"type":47,"tag":69,"props":135,"children":137},{"className":136},[],[138],{"type":53,"value":139},"pcie@N_status=…",{"type":53,"value":141}," (+ ",{"type":47,"tag":69,"props":143,"children":145},{"className":144},[],[146],{"type":53,"value":147},"pcie@N_max-link-speed",{"type":53,"value":149},", ",{"type":47,"tag":69,"props":151,"children":153},{"className":152},[],[154],{"type":53,"value":155},"pcie@N_pcie-mode",{"type":53,"value":149},{"type":47,"tag":69,"props":158,"children":160},{"className":159},[],[161],{"type":53,"value":162},"pcie@N_clk-scheme",{"type":53,"value":149},{"type":47,"tag":69,"props":165,"children":167},{"className":166},[],[168],{"type":53,"value":169},"pcie-cN-endpoint-enable",{"type":53,"value":171},")",{"type":47,"tag":129,"props":173,"children":174},{},[175,181],{"type":47,"tag":69,"props":176,"children":178},{"className":177},[],[179],{"type":53,"value":180},"\u002Fpcie\u002Fpcie@N",{"type":53,"value":182}," in BPMP DTB",{"type":47,"tag":129,"props":184,"children":185},{},[186],{"type":53,"value":187},"UPHY lane power, refclk gating, controller-side power rails",{"type":47,"tag":102,"props":189,"children":190},{},[191,202,213],{"type":47,"tag":129,"props":192,"children":193},{},[194,196],{"type":53,"value":195},"Kernel-DT overlay on ",{"type":47,"tag":69,"props":197,"children":199},{"className":198},[],[200],{"type":53,"value":201},"&pcieN",{"type":47,"tag":129,"props":203,"children":204},{},[205,211],{"type":47,"tag":69,"props":206,"children":208},{"className":207},[],[209],{"type":53,"value":210},"\u002Fbus@0\u002Fpcie@\u003Caddr>",{"type":53,"value":212}," in kernel DTB",{"type":47,"tag":129,"props":214,"children":215},{},[216],{"type":53,"value":217},"Kernel probe, lane width, link speed, RC\u002FEP mode",{"type":47,"tag":63,"props":219,"children":220},{},[221],{"type":53,"value":222},"Skipping the kernel overlay on a disable lets the kernel probe a\npowered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token\non a disable leaves BPMP holding the PHY hot.",{"type":47,"tag":63,"props":224,"children":225},{},[226,231,233,239],{"type":47,"tag":86,"props":227,"children":228},{},[229],{"type":53,"value":230},"Agentic, not table-driven",{"type":53,"value":232}," — no controller table, no\n",{"type":47,"tag":69,"props":234,"children":236},{"className":235},[],[237],{"type":53,"value":238},"questions.json",{"type":53,"value":240},". Every controller, lane width, schematic-routed\nreceptacle, and authoritative DT node address is discovered at runtime\nfrom the docs + DTB + carrier pinmap.",{"type":47,"tag":63,"props":242,"children":243},{},[244,246,251,253,259,261,267,269,279,281,287,289,295,297,303],{"type":53,"value":245},"The output is a ",{"type":47,"tag":86,"props":247,"children":248},{},[249],{"type":53,"value":250},"kernel-DT overlay commit only",{"type":53,"value":252},". Per-controller\n",{"type":47,"tag":69,"props":254,"children":256},{"className":255},[],[257],{"type":53,"value":258},"fragment@N",{"type":53,"value":260}," blocks are appended to the composite custom overlay\n",{"type":47,"tag":69,"props":262,"children":264},{"className":263},[],[265],{"type":53,"value":266},".dts",{"type":53,"value":268}," per\n",{"type":47,"tag":270,"props":271,"children":273},"a",{"href":272},"..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md",[274],{"type":47,"tag":69,"props":275,"children":277},{"className":276},[],[278],{"type":53,"value":272},{"type":53,"value":280},"\nand committed to the ",{"type":47,"tag":69,"props":282,"children":284},{"className":283},[],[285],{"type":53,"value":286},"bsp_sources\u002F",{"type":53,"value":288}," hardware repo.\n",{"type":47,"tag":69,"props":290,"children":292},{"className":291},[],[293],{"type":53,"value":294},"\u002Fjetson-build-source",{"type":53,"value":296}," compiles the composite to ",{"type":47,"tag":69,"props":298,"children":300},{"className":299},[],[301],{"type":53,"value":302},".dtbo",{"type":53,"value":304}," and owns its\nMakefile + flash-conf registration.",{"type":47,"tag":63,"props":306,"children":307},{},[308,321,323,328,329,334,335,340,342,347,348,353,355,361,363,369,371,377,379,385,387,393,395,401],{"type":47,"tag":86,"props":309,"children":310},{},[311,313,319],{"type":53,"value":312},"This skill MUST NOT edit ",{"type":47,"tag":69,"props":314,"children":316},{"className":315},[],[317],{"type":53,"value":318},"ODMDATA=\"...\"",{"type":53,"value":320},".",{"type":53,"value":322}," All ODMDATA tokens\n(",{"type":47,"tag":69,"props":324,"children":326},{"className":325},[],[327],{"type":53,"value":139},{"type":53,"value":149},{"type":47,"tag":69,"props":330,"children":332},{"className":331},[],[333],{"type":53,"value":147},{"type":53,"value":149},{"type":47,"tag":69,"props":336,"children":338},{"className":337},[],[339],{"type":53,"value":155},{"type":53,"value":341},",\n",{"type":47,"tag":69,"props":343,"children":345},{"className":344},[],[346],{"type":53,"value":162},{"type":53,"value":149},{"type":47,"tag":69,"props":349,"children":351},{"className":350},[],[352],{"type":53,"value":169},{"type":53,"value":354},", plus the\n",{"type":47,"tag":69,"props":356,"children":358},{"className":357},[],[359],{"type":53,"value":360},"uphyX-config-N",{"type":53,"value":362}," surface tokens and ",{"type":47,"tag":69,"props":364,"children":366},{"className":365},[],[367],{"type":53,"value":368},"UPHY_CONFIG=\"\"",{"type":53,"value":370}," clear) are\nemitted by ",{"type":47,"tag":69,"props":372,"children":374},{"className":373},[],[375],{"type":53,"value":376},"\u002Fjetson-customize-uphy",{"type":53,"value":378}," in a single atomic commit on the\ncarrier flash-conf fork. The allocation table this skill consumes\nfrom the UPHY sidecar already tells the operator which controllers\nare ",{"type":47,"tag":69,"props":380,"children":382},{"className":381},[],[383],{"type":53,"value":384},"okay",{"type":53,"value":386}," \u002F ",{"type":47,"tag":69,"props":388,"children":390},{"className":389},[],[391],{"type":53,"value":392},"disabled",{"type":53,"value":394}," \u002F per-lane sized; this skill only translates\nthat table into kernel-DT overlay fragments and verifies that the\noverlay agrees with the ODMDATA already committed by ",{"type":47,"tag":69,"props":396,"children":398},{"className":397},[],[399],{"type":53,"value":400},"customize-uphy",{"type":53,"value":402},"\n(consistency check in Step 8 — disagreement is reported, not silently\nfixed).",{"type":47,"tag":56,"props":404,"children":406},{"id":405},"when-to-invoke",[407],{"type":53,"value":408},"When to invoke",{"type":47,"tag":410,"props":411,"children":412},"ul",{},[413,427,432,459],{"type":47,"tag":414,"props":415,"children":416},"li",{},[417,419,425],{"type":53,"value":418},"The user says \"configure PCIe\", \"enable PCIe controller\", \"set PCIe\nnum-lanes\", \"change PCIe link speed\", or asks to flip a\n",{"type":47,"tag":69,"props":420,"children":422},{"className":421},[],[423],{"type":53,"value":424},"pcie@N_status",{"type":53,"value":426}," token.",{"type":47,"tag":414,"props":428,"children":429},{},[430],{"type":53,"value":431},"A specific PCIe slot or M.2 receptacle doesn't enumerate after\nflash, OR the link trains at the wrong width \u002F speed.",{"type":47,"tag":414,"props":433,"children":434},{},[435,441,443,449,451,457],{"type":47,"tag":69,"props":436,"children":438},{"className":437},[],[439],{"type":53,"value":440},"jetson-customize-uphy",{"type":53,"value":442}," ran and re-allocated lanes across PCIe controllers\n(e.g. switched from ",{"type":47,"tag":69,"props":444,"children":446},{"className":445},[],[447],{"type":53,"value":448},"uphy0-config-7",{"type":53,"value":450}," to ",{"type":47,"tag":69,"props":452,"children":454},{"className":453},[],[455],{"type":53,"value":456},"uphy0-config-6",{"type":53,"value":458}," enabling\nPCIe C3); the per-controller side now needs to be brought up.",{"type":47,"tag":414,"props":460,"children":461},{},[462,468],{"type":47,"tag":69,"props":463,"children":465},{"className":464},[],[466],{"type":53,"value":467},"jetson-customize-mgbe",{"type":53,"value":469}," reports the QSFP path is wired but the kernel\ndoesn't probe its PCIe-side companion (rare; XFI configurations).",{"type":47,"tag":63,"props":471,"children":472},{},[473],{"type":47,"tag":86,"props":474,"children":475},{},[476],{"type":53,"value":477},"Prerequisites:",{"type":47,"tag":410,"props":479,"children":480},{},[481,502,521,532,558,563,596],{"type":47,"tag":414,"props":482,"children":483},{},[484,486,492,494,500],{"type":53,"value":485},"Active profile with ",{"type":47,"tag":69,"props":487,"children":489},{"className":488},[],[490],{"type":53,"value":491},"reference_devkit:",{"type":53,"value":493}," + ",{"type":47,"tag":69,"props":495,"children":497},{"className":496},[],[498],{"type":53,"value":499},"custom_carrier:",{"type":53,"value":501}," blocks.",{"type":47,"tag":414,"props":503,"children":504},{},[505,511,513,519],{"type":47,"tag":69,"props":506,"children":508},{"className":507},[],[509],{"type":53,"value":510},"\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git",{"type":53,"value":512}," exists\n(",{"type":47,"tag":69,"props":514,"children":516},{"className":515},[],[517],{"type":53,"value":518},"\u002Fjetson-init-source",{"type":53,"value":520},").",{"type":47,"tag":414,"props":522,"children":523},{},[524,530],{"type":47,"tag":69,"props":525,"children":527},{"className":526},[],[528],{"type":53,"value":529},"\u002Fjetson-derive-carrier",{"type":53,"value":531}," has run — carrier flash-conf fork is in\nthe overlay tracker.",{"type":47,"tag":414,"props":533,"children":534},{},[535,540,542,548,550,556],{"type":47,"tag":69,"props":536,"children":538},{"className":537},[],[539],{"type":53,"value":376},{"type":53,"value":541}," has run — its JSON sidecar at\n",{"type":47,"tag":69,"props":543,"children":545},{"className":544},[],[546],{"type":53,"value":547},"\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-uphy.json",{"type":53,"value":549},"\ndrives the per-controller ",{"type":47,"tag":69,"props":551,"children":553},{"className":552},[],[554],{"type":53,"value":555},"enable",{"type":53,"value":557}," decision.",{"type":47,"tag":414,"props":559,"children":560},{},[561],{"type":53,"value":562},"Source-of-truth docs registered or supplied at prompt: Adaptation\nGuide, Module Design Guide, SoC TRM.",{"type":47,"tag":414,"props":564,"children":565},{},[566,594],{"type":47,"tag":86,"props":567,"children":568},{},[569,571,576,578,584,586,592],{"type":53,"value":570},"When ",{"type":47,"tag":69,"props":572,"children":574},{"className":573},[],[575],{"type":53,"value":499},{"type":53,"value":577}," is present, both\n",{"type":47,"tag":69,"props":579,"children":581},{"className":580},[],[582],{"type":53,"value":583},"documents.custom_carrier_schematic",{"type":53,"value":585}," AND\n",{"type":47,"tag":69,"props":587,"children":589},{"className":588},[],[590],{"type":53,"value":591},"documents.custom_carrier_pinmux_xls",{"type":53,"value":593}," are REQUIRED.",{"type":53,"value":595}," Refuse the run\nif either is missing — routing on a custom carrier cannot be guessed.\nReference-devkit-only profiles skip this check.",{"type":47,"tag":414,"props":597,"children":598},{},[599,605],{"type":47,"tag":69,"props":600,"children":602},{"className":601},[],[603],{"type":53,"value":604},"dtc",{"type":53,"value":606}," on PATH.",{"type":47,"tag":56,"props":608,"children":610},{"id":609},"procedure-summary",[611],{"type":53,"value":612},"Procedure (summary)",{"type":47,"tag":63,"props":614,"children":615},{},[616,618,627],{"type":53,"value":617},"Full step-by-step walkthrough lives in\n",{"type":47,"tag":270,"props":619,"children":621},{"href":620},"references\u002Fprocedure.md",[622],{"type":47,"tag":69,"props":623,"children":625},{"className":624},[],[626],{"type":53,"value":620},{"type":53,"value":628},". High-level flow:",{"type":47,"tag":630,"props":631,"children":632},"ol",{},[633,667,687,698,733,782,882,887,905],{"type":47,"tag":414,"props":634,"children":635},{},[636,638,644,645,651,652,658,660,665],{"type":53,"value":637},"Resolve active target + open source-of-truth documents (incl.\n",{"type":47,"tag":69,"props":639,"children":641},{"className":640},[],[642],{"type":53,"value":643},"\u003Ccarrier-pinmap>",{"type":53,"value":149},{"type":47,"tag":69,"props":646,"children":648},{"className":647},[],[649],{"type":53,"value":650},"\u003Cref-dtb>",{"type":53,"value":149},{"type":47,"tag":69,"props":653,"children":655},{"className":654},[],[656],{"type":53,"value":657},"\u003Cuphy-state>",{"type":53,"value":659},"). Refuse if\n",{"type":47,"tag":69,"props":661,"children":663},{"className":662},[],[664],{"type":53,"value":657},{"type":53,"value":666}," is missing.",{"type":47,"tag":414,"props":668,"children":669},{},[670,672,677,679,685],{"type":53,"value":671},"Diff PCIe topology — devkit vs custom carrier — by decompiling\n",{"type":47,"tag":69,"props":673,"children":675},{"className":674},[],[676],{"type":53,"value":650},{"type":53,"value":678}," and grepping the schematic for ",{"type":47,"tag":69,"props":680,"children":682},{"className":681},[],[683],{"type":53,"value":684},"PEX\u003CN>_*",{"type":53,"value":686}," net labels.",{"type":47,"tag":414,"props":688,"children":689},{},[690,696],{"type":47,"tag":69,"props":691,"children":693},{"className":692},[],[694],{"type":53,"value":695},"AskUserQuestion",{"type":53,"value":697}," (multiSelect) — which controllers to customize.",{"type":47,"tag":414,"props":699,"children":700},{},[701,703,709,711,717,718,724,726,732],{"type":53,"value":702},"Per-controller verification: pinmap + schematic + ",{"type":47,"tag":69,"props":704,"children":706},{"className":705},[],[707],{"type":53,"value":708},"pin_verifier.py",{"type":53,"value":710},"\nfor ",{"type":47,"tag":69,"props":712,"children":714},{"className":713},[],[715],{"type":53,"value":716},"PE\u003CN>_CLKREQ_L",{"type":53,"value":149},{"type":47,"tag":69,"props":719,"children":721},{"className":720},[],[722],{"type":53,"value":723},"PE\u003CN>_RST_L",{"type":53,"value":725},", optional ",{"type":47,"tag":69,"props":727,"children":729},{"className":728},[],[730],{"type":53,"value":731},"PE\u003CN>_WAKE_L",{"type":53,"value":320},{"type":47,"tag":414,"props":734,"children":735},{},[736,738,743,745,750,751,757,758,764,766,772,774,780],{"type":53,"value":737},"Auto-derive per-controller plan (",{"type":47,"tag":69,"props":739,"children":741},{"className":740},[],[742],{"type":53,"value":555},{"type":53,"value":744}," from ",{"type":47,"tag":69,"props":746,"children":748},{"className":747},[],[749],{"type":53,"value":657},{"type":53,"value":341},{"type":47,"tag":69,"props":752,"children":754},{"className":753},[],[755],{"type":53,"value":756},"lanes",{"type":53,"value":386},{"type":47,"tag":69,"props":759,"children":761},{"className":760},[],[762],{"type":53,"value":763},"speed",{"type":53,"value":765}," from Adaptation Guide, ",{"type":47,"tag":69,"props":767,"children":769},{"className":768},[],[770],{"type":53,"value":771},"mode",{"type":53,"value":773}," hard-pinned to\n",{"type":47,"tag":69,"props":775,"children":777},{"className":776},[],[778],{"type":53,"value":779},"\"rc\"",{"type":53,"value":781},") → mandatory confirm-or-customize gate.",{"type":47,"tag":414,"props":783,"children":784},{},[785,787,792,794,800,802,807,809,814,816,821,822,828,830,841,843,848,850,855,856,861,862,867,868,873,875,880],{"type":53,"value":786},"Append per-controller ",{"type":47,"tag":69,"props":788,"children":790},{"className":789},[],[791],{"type":53,"value":258},{"type":53,"value":793}," blocks (marker\n",{"type":47,"tag":69,"props":795,"children":797},{"className":796},[],[798],{"type":53,"value":799},"\u002F* custom-bsp: pcie:pcie@\u003Caddr> *\u002F",{"type":53,"value":801},") to the composite custom\noverlay ",{"type":47,"tag":69,"props":803,"children":805},{"className":804},[],[806],{"type":53,"value":266},{"type":53,"value":808}," in ",{"type":47,"tag":69,"props":810,"children":812},{"className":811},[],[813],{"type":53,"value":286},{"type":53,"value":815},". Pre-flight ",{"type":47,"tag":69,"props":817,"children":819},{"className":818},[],[820],{"type":53,"value":604},{"type":53,"value":493},{"type":47,"tag":69,"props":823,"children":825},{"className":824},[],[826],{"type":53,"value":827},"fdtoverlay",{"type":53,"value":829},".\nCommit via the workflow's preview gate.\n",{"type":47,"tag":86,"props":831,"children":832},{},[833,835],{"type":53,"value":834},"Do not edit ",{"type":47,"tag":69,"props":836,"children":838},{"className":837},[],[839],{"type":53,"value":840},"ODMDATA",{"type":53,"value":842}," — ",{"type":47,"tag":69,"props":844,"children":846},{"className":845},[],[847],{"type":53,"value":376},{"type":53,"value":849}," already emitted\n",{"type":47,"tag":69,"props":851,"children":853},{"className":852},[],[854],{"type":53,"value":139},{"type":53,"value":149},{"type":47,"tag":69,"props":857,"children":859},{"className":858},[],[860],{"type":53,"value":147},{"type":53,"value":149},{"type":47,"tag":69,"props":863,"children":865},{"className":864},[],[866],{"type":53,"value":155},{"type":53,"value":341},{"type":47,"tag":69,"props":869,"children":871},{"className":870},[],[872],{"type":53,"value":162},{"type":53,"value":874},", and ",{"type":47,"tag":69,"props":876,"children":878},{"className":877},[],[879],{"type":53,"value":169},{"type":53,"value":881}," in its single\natomic ODMDATA commit. This skill only translates the per-controller\nplan into kernel-DT overlay fragments.",{"type":47,"tag":414,"props":883,"children":884},{},[885],{"type":53,"value":886},"(Step folded into Step 6 — overlay-only emission.)",{"type":47,"tag":414,"props":888,"children":889},{},[890,892],{"type":53,"value":891},"Cross-check ODMDATA vs overlay consistency. On a contradictory\nrow, ",{"type":47,"tag":86,"props":893,"children":894},{},[895,897,903],{"type":53,"value":896},"stop and ask the user how to recover the two commits.\nNever run ",{"type":47,"tag":69,"props":898,"children":900},{"className":899},[],[901],{"type":53,"value":902},"git reset --hard",{"type":53,"value":904}," autonomously.",{"type":47,"tag":414,"props":906,"children":907},{},[908,910,916],{"type":53,"value":909},"Write run-state JSON sidecar at\n",{"type":47,"tag":69,"props":911,"children":913},{"className":912},[],[914],{"type":53,"value":915},"\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-pcie.json",{"type":47,"tag":410,"props":917,"children":918},{},[919],{"type":47,"tag":414,"props":920,"children":921},{},[922,924,929,931,936],{"type":53,"value":923},"summary, then drive the downstream next-step chain via sequential\n",{"type":47,"tag":69,"props":925,"children":927},{"className":926},[],[928],{"type":53,"value":695},{"type":53,"value":930}," prompts per ",{"type":47,"tag":69,"props":932,"children":934},{"className":933},[],[935],{"type":53,"value":620},{"type":53,"value":937}," Step 9.\nNever substitute a printed \"Next step: …\" line for the prompts.",{"type":47,"tag":56,"props":939,"children":941},{"id":940},"limitations",[942],{"type":53,"value":943},"Limitations",{"type":47,"tag":410,"props":945,"children":946},{},[947,965,993,1018,1035],{"type":47,"tag":414,"props":948,"children":949},{},[950,955,957,963],{"type":47,"tag":86,"props":951,"children":952},{},[953],{"type":53,"value":954},"Mode hard-pinned to RC.",{"type":53,"value":956}," Endpoint mode is only emitted when the\noperator passes ",{"type":47,"tag":69,"props":958,"children":960},{"className":959},[],[961],{"type":53,"value":962},"mode_override=\"ep\"",{"type":53,"value":964}," in Step 5c.",{"type":47,"tag":414,"props":966,"children":967},{},[968,978,980,985,987,992],{"type":47,"tag":86,"props":969,"children":970},{},[971,976],{"type":47,"tag":69,"props":972,"children":974},{"className":973},[],[975],{"type":53,"value":555},{"type":53,"value":977}," is derived, not asked.",{"type":53,"value":979}," UPHY-allocated controllers are\nmandatorily ",{"type":47,"tag":69,"props":981,"children":983},{"className":982},[],[984],{"type":53,"value":384},{"type":53,"value":986},"; non-allocated are mandatorily ",{"type":47,"tag":69,"props":988,"children":990},{"className":989},[],[991],{"type":53,"value":392},{"type":53,"value":320},{"type":47,"tag":414,"props":994,"children":995},{},[996,1001,1003,1009,1011,1016],{"type":47,"tag":86,"props":997,"children":998},{},[999],{"type":53,"value":1000},"No upstream BSP edits.",{"type":53,"value":1002}," Output lands in ",{"type":47,"tag":69,"props":1004,"children":1006},{"className":1005},[],[1007],{"type":53,"value":1008},"Linux_for_Tegra\u002F",{"type":53,"value":1010}," +\n",{"type":47,"tag":69,"props":1012,"children":1014},{"className":1013},[],[1015],{"type":53,"value":286},{"type":53,"value":1017}," only.",{"type":47,"tag":414,"props":1019,"children":1020},{},[1021,1026,1028,1033],{"type":47,"tag":86,"props":1022,"children":1023},{},[1024],{"type":53,"value":1025},"Pre-flight overlay merge is a sanity check",{"type":53,"value":1027},", not the production\nbuild. ",{"type":47,"tag":69,"props":1029,"children":1031},{"className":1030},[],[1032],{"type":53,"value":294},{"type":53,"value":1034}," is authoritative.",{"type":47,"tag":414,"props":1036,"children":1037},{},[1038,1043,1045,1050],{"type":47,"tag":86,"props":1039,"children":1040},{},[1041],{"type":53,"value":1042},"Flash-conf overlay registration is out of scope.",{"type":53,"value":1044}," Owned by\n",{"type":47,"tag":69,"props":1046,"children":1048},{"className":1047},[],[1049],{"type":53,"value":294},{"type":53,"value":1051}," Step 5.0a.",{"type":47,"tag":56,"props":1053,"children":1055},{"id":1054},"troubleshooting",[1056],{"type":53,"value":1057},"Troubleshooting",{"type":47,"tag":410,"props":1059,"children":1060},{},[1061,1083,1118,1143,1159,1176],{"type":47,"tag":414,"props":1062,"children":1063},{},[1064,1074,1076,1081],{"type":47,"tag":86,"props":1065,"children":1066},{},[1067,1072],{"type":47,"tag":69,"props":1068,"children":1070},{"className":1069},[],[1071],{"type":53,"value":657},{"type":53,"value":1073}," missing",{"type":53,"value":1075}," → run ",{"type":47,"tag":69,"props":1077,"children":1079},{"className":1078},[],[1080],{"type":53,"value":376},{"type":53,"value":1082}," first.",{"type":47,"tag":414,"props":1084,"children":1085},{},[1086,1091,1093,1099,1101,1107,1109,1117],{"type":47,"tag":86,"props":1087,"children":1088},{},[1089],{"type":53,"value":1090},"Slot doesn't enumerate after flash",{"type":53,"value":1092}," → check ",{"type":47,"tag":69,"props":1094,"children":1096},{"className":1095},[],[1097],{"type":53,"value":1098},"dmesg | grep pcie",{"type":53,"value":1100},";\nre-verify ODMDATA ",{"type":47,"tag":69,"props":1102,"children":1104},{"className":1103},[],[1105],{"type":53,"value":1106},"pcie@\u003CN>_status=okay",{"type":53,"value":1108}," and the overlay fragment\nagree (Step 8 table in\n",{"type":47,"tag":270,"props":1110,"children":1111},{"href":620},[1112],{"type":47,"tag":69,"props":1113,"children":1115},{"className":1114},[],[1116],{"type":53,"value":620},{"type":53,"value":520},{"type":47,"tag":414,"props":1119,"children":1120},{},[1121,1126,1128,1133,1135,1141],{"type":47,"tag":86,"props":1122,"children":1123},{},[1124],{"type":53,"value":1125},"Link trains at wrong width",{"type":53,"value":1127}," → confirm UPHY config in\n",{"type":47,"tag":69,"props":1129,"children":1131},{"className":1130},[],[1132],{"type":53,"value":657},{"type":53,"value":1134}," allocates the expected lane count; the kernel\nfragment's ",{"type":47,"tag":69,"props":1136,"children":1138},{"className":1137},[],[1139],{"type":53,"value":1140},"num-lanes",{"type":53,"value":1142}," must match.",{"type":47,"tag":414,"props":1144,"children":1145},{},[1146,1157],{"type":47,"tag":86,"props":1147,"children":1148},{},[1149,1155],{"type":47,"tag":69,"props":1150,"children":1152},{"className":1151},[],[1153],{"type":53,"value":1154},"compatible",{"type":53,"value":1156}," mismatch",{"type":53,"value":1158}," → fix the composite root, not the\nfragment. UEFI plugin-manager silently skips on mismatch.",{"type":47,"tag":414,"props":1160,"children":1161},{},[1162,1167,1169,1174],{"type":47,"tag":86,"props":1163,"children":1164},{},[1165],{"type":53,"value":1166},"Contradictory ODMDATA-vs-overlay row",{"type":53,"value":1168}," → ask the user; do not\nauto-",{"type":47,"tag":69,"props":1170,"children":1172},{"className":1171},[],[1173],{"type":53,"value":902},{"type":53,"value":1175},". See gotchas.",{"type":47,"tag":414,"props":1177,"children":1178},{},[1179,1184,1186,1195,1197,1202],{"type":47,"tag":86,"props":1180,"children":1181},{},[1182],{"type":53,"value":1183},"Common pitfalls",{"type":53,"value":1185}," — see\n",{"type":47,"tag":270,"props":1187,"children":1189},{"href":1188},"references\u002Fgotchas.md",[1190],{"type":47,"tag":69,"props":1191,"children":1193},{"className":1192},[],[1194],{"type":53,"value":1188},{"type":53,"value":1196}," (RC pinning, node-\naddress sourcing, stock-disabled controllers, intra-file handoff\nwith ",{"type":47,"tag":69,"props":1198,"children":1200},{"className":1199},[],[1201],{"type":53,"value":440},{"type":53,"value":520},{"type":47,"tag":56,"props":1204,"children":1206},{"id":1205},"references",[1207],{"type":53,"value":1208},"References",{"type":47,"tag":410,"props":1210,"children":1211},{},[1212,1225,1246,1260,1282,1297,1310,1330,1344,1366,1380],{"type":47,"tag":414,"props":1213,"children":1214},{},[1215,1223],{"type":47,"tag":270,"props":1216,"children":1217},{"href":620},[1218],{"type":47,"tag":69,"props":1219,"children":1221},{"className":1220},[],[1222],{"type":53,"value":620},{"type":53,"value":1224}," — full nine-\nstep procedure (topology diff, plan derivation, overlay append,\nODMDATA cross-check, sidecar).",{"type":47,"tag":414,"props":1226,"children":1227},{},[1228,1236,1238],{"type":47,"tag":270,"props":1229,"children":1230},{"href":1188},[1231],{"type":47,"tag":69,"props":1232,"children":1234},{"className":1233},[],[1235],{"type":53,"value":1188},{"type":53,"value":1237}," — failure modes\n",{"type":47,"tag":410,"props":1239,"children":1240},{},[1241],{"type":47,"tag":414,"props":1242,"children":1243},{},[1244],{"type":53,"value":1245},"invariants (RC pinning, address sourcing, BPMP handoff).",{"type":47,"tag":414,"props":1247,"children":1248},{},[1249,1258],{"type":47,"tag":270,"props":1250,"children":1252},{"href":1251},"..\u002F..\u002Fscripts\u002Fpin_verifier.py",[1253],{"type":47,"tag":69,"props":1254,"children":1256},{"className":1255},[],[1257],{"type":53,"value":1251},{"type":53,"value":1259},"\n— shared HSIO pin verifier (Step 4).",{"type":47,"tag":414,"props":1261,"children":1262},{},[1263,1272,1274,1280],{"type":47,"tag":270,"props":1264,"children":1266},{"href":1265},"..\u002F..\u002Freferences\u002Fplatform_template.yaml",[1267],{"type":47,"tag":69,"props":1268,"children":1270},{"className":1269},[],[1271],{"type":53,"value":1265},{"type":53,"value":1273},"\n— ",{"type":47,"tag":69,"props":1275,"children":1277},{"className":1276},[],[1278],{"type":53,"value":1279},"documents:",{"type":53,"value":1281}," block consumed by Step 1.",{"type":47,"tag":414,"props":1283,"children":1284},{},[1285,1295],{"type":47,"tag":270,"props":1286,"children":1288},{"href":1287},"..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants",[1289],{"type":47,"tag":69,"props":1290,"children":1292},{"className":1291},[],[1293],{"type":53,"value":1294},"..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md",{"type":53,"value":1296},"\n— overlay edit protocol + commit message preview gate.",{"type":47,"tag":414,"props":1298,"children":1299},{},[1300,1308],{"type":47,"tag":270,"props":1301,"children":1302},{"href":272},[1303],{"type":47,"tag":69,"props":1304,"children":1306},{"className":1305},[],[1307],{"type":53,"value":272},{"type":53,"value":1309},"\n— composite overlay filename \u002F skeleton \u002F append protocol.",{"type":47,"tag":414,"props":1311,"children":1312},{},[1313,1322,1324,1329],{"type":47,"tag":270,"props":1314,"children":1316},{"href":1315},"..\u002Fjetson-customize-uphy\u002FSKILL.md",[1317],{"type":47,"tag":69,"props":1318,"children":1320},{"className":1319},[],[1321],{"type":53,"value":1315},{"type":53,"value":1323},"\n— sibling skill that owns UPHY lane allocation; its sidecar drives\nthe per-controller ",{"type":47,"tag":69,"props":1325,"children":1327},{"className":1326},[],[1328],{"type":53,"value":555},{"type":53,"value":557},{"type":47,"tag":414,"props":1331,"children":1332},{},[1333,1342],{"type":47,"tag":270,"props":1334,"children":1336},{"href":1335},"..\u002Fjetson-customize-pinmux\u002FSKILL.md",[1337],{"type":47,"tag":69,"props":1338,"children":1340},{"className":1339},[],[1341],{"type":53,"value":1335},{"type":53,"value":1343},"\n— sibling skill invoked by Step 4 (with operator confirmation) to\nfix HSIO pin SFIO mismatches.",{"type":47,"tag":414,"props":1345,"children":1346},{},[1347,1356,1358],{"type":47,"tag":270,"props":1348,"children":1350},{"href":1349},"..\u002Fjetson-customize-mgbe\u002FSKILL.md",[1351],{"type":47,"tag":69,"props":1352,"children":1354},{"className":1353},[],[1355],{"type":53,"value":1349},{"type":53,"value":1357},"\n— sibling for MGBE controllers; shares the two-surface (ODMDATA\n",{"type":47,"tag":410,"props":1359,"children":1360},{},[1361],{"type":47,"tag":414,"props":1362,"children":1363},{},[1364],{"type":53,"value":1365},"overlay) pattern.",{"type":47,"tag":414,"props":1367,"children":1368},{},[1369,1378],{"type":47,"tag":270,"props":1370,"children":1372},{"href":1371},"..\u002Fjetson-derive-carrier\u002FSKILL.md",[1373],{"type":47,"tag":69,"props":1374,"children":1376},{"className":1375},[],[1377],{"type":53,"value":1371},{"type":53,"value":1379},"\n— must run first; produces the carrier flash-conf fork edited in\nStep 6.",{"type":47,"tag":414,"props":1381,"children":1382},{},[1383,1392],{"type":47,"tag":270,"props":1384,"children":1386},{"href":1385},"..\u002Fjetson-init-source\u002FSKILL.md",[1387],{"type":47,"tag":69,"props":1388,"children":1390},{"className":1389},[],[1391],{"type":53,"value":1385},{"type":53,"value":1393},"\n— produces the overlay tracker + bsp_sources repo this skill\ncommits into.",{"items":1395,"total":1499},[1396,1413,1427,1441,1453,1470,1485],{"slug":1397,"name":1397,"fn":1398,"description":1399,"org":1400,"tags":1401,"stars":20,"repoUrl":21,"updatedAt":1412},"accelerated-computing-cudf","accelerate data processing with cuDF","Official NVIDIA-authored guidance for NVIDIA cuDF GPU DataFrames, pandas acceleration, dask-cuDF, ETL, joins, groupby, CSV\u002FParquet I\u002FO, nullable semantics, and multi-GPU DataFrame workloads.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1402,1405,1408,1409],{"name":1403,"slug":1404,"type":15},"Data Analysis","data-analysis",{"name":1406,"slug":1407,"type":15},"Data Engineering","data-engineering",{"name":9,"slug":8,"type":15},{"name":1410,"slug":1411,"type":15},"Performance","performance","2026-07-14T05:28:43.176466",{"slug":1414,"name":1414,"fn":1415,"description":1416,"org":1417,"tags":1418,"stars":20,"repoUrl":21,"updatedAt":1426},"aiq-deploy","deploy and manage NVIDIA AI-Q infrastructure","Use when asked to install, deploy, run, validate, troubleshoot, or stop NVIDIA AI-Q Blueprint infrastructure.\n",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1419,1422,1425],{"name":1420,"slug":1421,"type":15},"Deployment","deployment",{"name":1423,"slug":1424,"type":15},"Infrastructure","infrastructure",{"name":9,"slug":8,"type":15},"2026-07-14T05:29:06.667109",{"slug":1428,"name":1428,"fn":1429,"description":1430,"org":1431,"tags":1432,"stars":20,"repoUrl":21,"updatedAt":1440},"aiq-research","conduct deep research with AI-Q","Use when asked to run deep research or AI-Q research through a reachable NVIDIA AI-Q Blueprint backend.\n",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1433,1436,1437],{"name":1434,"slug":1435,"type":15},"Agents","agents",{"name":9,"slug":8,"type":15},{"name":1438,"slug":1439,"type":15},"Research","research","2026-07-14T05:28:06.816956",{"slug":1442,"name":1442,"fn":1443,"description":1444,"org":1445,"tags":1446,"stars":20,"repoUrl":21,"updatedAt":1452},"amc-run-sample-calibration","run AMC sample dataset calibration","Run end-to-end calibration on the shipped sample dataset (sdg_08_2_sample_data_010926.zip) against a running AMC microservice. Use when user says 'test sample dataset', 'run sample calibration', 'verify AMC install', or 'launch and test'.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1447,1448,1449],{"name":1403,"slug":1404,"type":15},{"name":9,"slug":8,"type":15},{"name":1450,"slug":1451,"type":15},"Testing","testing","2026-07-17T05:29:03.913266",{"slug":1454,"name":1454,"fn":1455,"description":1456,"org":1457,"tags":1458,"stars":20,"repoUrl":21,"updatedAt":1469},"amc-run-video-calibration","calibrate video datasets with AutoMagicCalib","Calibrate a new dataset from pre-recorded video files via the AutoMagicCalib REST API. Use when user has local MP4s and says 'calibrate my videos', 'run AMC on these videos', or similar. For RTSP\u002Flive streams, use amc-run-rtsp-calibration instead.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1459,1462,1465,1466],{"name":1460,"slug":1461,"type":15},"Automation","automation",{"name":1463,"slug":1464,"type":15},"Imaging","imaging",{"name":9,"slug":8,"type":15},{"name":1467,"slug":1468,"type":15},"Video","video","2026-07-17T05:28:53.905004",{"slug":1471,"name":1471,"fn":1472,"description":1473,"org":1474,"tags":1475,"stars":20,"repoUrl":21,"updatedAt":1484},"amc-setup-calibration-stack","deploy AutoMagicCalib microservice with Docker","Launch AutoMagicCalib microservice and web UI from NGC release images via Docker Compose. Use when user says 'deploy auto calibration', 'launch auto calibration', 'launch AMC', 'start MS+UI', or 'set up auto-magic-calib'. Requires NGC API key.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1476,1477,1480,1481],{"name":1420,"slug":1421,"type":15},{"name":1478,"slug":1479,"type":15},"Docker","docker",{"name":9,"slug":8,"type":15},{"name":1482,"slug":1483,"type":15},"Operations","operations","2026-07-17T05:28:56.913999",{"slug":1486,"name":1486,"fn":1487,"description":1488,"org":1489,"tags":1490,"stars":20,"repoUrl":21,"updatedAt":1498},"cudaq-guide","develop quantum applications with CUDA-Q","CUDA-Q onboarding guide for installation, test programs, GPU simulation, QPU hardware, and quantum applications.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1491,1492,1495],{"name":9,"slug":8,"type":15},{"name":1493,"slug":1494,"type":15},"Quantum Computing","quantum-computing",{"name":1496,"slug":1497,"type":15},"Simulation","simulation","2026-07-14T05:26:58.898253",305,{"items":1501,"total":1652},[1502,1520,1536,1547,1559,1573,1586,1600,1611,1620,1634,1643],{"slug":1503,"name":1503,"fn":1504,"description":1505,"org":1506,"tags":1507,"stars":1517,"repoUrl":1518,"updatedAt":1519},"nemoclaw-user-guide","retrieve NemoClaw documentation and configuration","Guides human users' AI agents to the NemoClaw docs MCP server and canonical Fern documentation in Markdown form. Use when users ask how to install, configure, operate, troubleshoot, secure, or learn NemoClaw with an AI coding assistant. Trigger keywords - nemoclaw docs, use nemoclaw with ai agent, nemoclaw mcp docs, nemoclaw install help, nemoclaw quickstart, nemoclaw markdown docs, llms.txt, agent skills.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1508,1511,1514],{"name":1509,"slug":1510,"type":15},"Documentation","documentation",{"name":1512,"slug":1513,"type":15},"MCP","mcp",{"name":1515,"slug":1516,"type":15},"Search","search",21777,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FNemoClaw","2026-07-20T06:00:01.461044",{"slug":1521,"name":1521,"fn":1522,"description":1523,"org":1524,"tags":1525,"stars":1533,"repoUrl":1534,"updatedAt":1535},"mcore-build-and-dependency","manage Megatron-LM development environments","Container-based dev environment setup and dependency management for Megatron-LM. Covers acquiring and launching the CI container, uv package management, and updating uv.lock.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1526,1529,1530],{"name":1527,"slug":1528,"type":15},"Containers","containers",{"name":1420,"slug":1421,"type":15},{"name":1531,"slug":1532,"type":15},"Python","python",17049,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FMegatron-LM","2026-07-27T06:06:11.249662",{"slug":1537,"name":1537,"fn":1538,"description":1539,"org":1540,"tags":1541,"stars":1533,"repoUrl":1534,"updatedAt":1546},"mcore-bump-base-image","update NVIDIA PyTorch base images","Bump the NVIDIA PyTorch base image (`nvcr.io\u002Fnvidia\u002Fpytorch:YY.MM-py3`) used by Megatron-LM CI. Covers the two pin sites (GitHub CI in `docker\u002F.ngc_version.dev` and GitLab CI in `.gitlab\u002Fstages\u002F01.build.yml`), the post-bump CI loop (re-run functional tests, refresh golden values, mark broken tests), and the gotchas that bit PRs",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1542,1545],{"name":1543,"slug":1544,"type":15},"CI\u002FCD","ci-cd",{"name":1420,"slug":1421,"type":15},"2026-07-14T05:25:59.97109",{"slug":1548,"name":1548,"fn":1549,"description":1550,"org":1551,"tags":1552,"stars":1533,"repoUrl":1534,"updatedAt":1558},"mcore-cicd","manage CI\u002FCD pipelines for Megatron-LM","CI\u002FCD reference for Megatron-LM. Covers CI pipeline structure, PR scope labels, triggering internal GitLab CI (which force-pushes the current branch to a pull-request\u002FBRANCH ref — always dry-run and verify the destination first; never run against shared or protected branches), and CI failure investigation.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1553,1554,1555],{"name":1543,"slug":1544,"type":15},{"name":1420,"slug":1421,"type":15},{"name":1556,"slug":1557,"type":15},"GitHub","github","2026-07-27T06:06:12.278222",{"slug":1560,"name":1560,"fn":1561,"description":1562,"org":1563,"tags":1564,"stars":1533,"repoUrl":1534,"updatedAt":1572},"mcore-create-issue","investigate CI failures and create issues","Investigate a failing GitHub Actions run or job and create a GitHub issue for the failure.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1565,1568,1569],{"name":1566,"slug":1567,"type":15},"Debugging","debugging",{"name":1556,"slug":1557,"type":15},{"name":1570,"slug":1571,"type":15},"Triage","triage","2026-07-14T05:25:57.442089",{"slug":1574,"name":1574,"fn":1575,"description":1576,"org":1577,"tags":1578,"stars":1533,"repoUrl":1534,"updatedAt":1585},"mcore-linting-and-formatting","lint and format Megatron-LM code","Linting and formatting for Megatron-LM. Covers running autoformat.sh, tools (ruff, black, isort, pylint, mypy), and code style rules.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1579,1582],{"name":1580,"slug":1581,"type":15},"Best Practices","best-practices",{"name":1583,"slug":1584,"type":15},"Code Analysis","code-analysis","2026-07-14T05:25:56.18433",{"slug":1587,"name":1587,"fn":1588,"description":1589,"org":1590,"tags":1591,"stars":1533,"repoUrl":1534,"updatedAt":1599},"mcore-migrate-gpt-to-hybrid","migrate Megatron-LM models to HybridModel","Migration guide for moving Megatron Core GPTModel checkpoints, model providers, training commands, and layer mappings to HybridModel.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1592,1595,1598],{"name":1593,"slug":1594,"type":15},"Machine Learning","machine-learning",{"name":1596,"slug":1597,"type":15},"Migration","migration",{"name":9,"slug":8,"type":15},"2026-07-17T06:07:11.777011",{"slug":1601,"name":1601,"fn":1602,"description":1603,"org":1604,"tags":1605,"stars":1533,"repoUrl":1534,"updatedAt":1610},"mcore-onboard-gb200-1node-tests","onboard functional tests for GB200","Onboard 1-node GitHub MR functional tests for GB200 from existing mr-scoped 2-node tests.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1606,1609],{"name":1607,"slug":1608,"type":15},"QA","qa",{"name":1450,"slug":1451,"type":15},"2026-07-14T05:25:53.673039",{"slug":1612,"name":1612,"fn":1613,"description":1614,"org":1615,"tags":1616,"stars":1533,"repoUrl":1534,"updatedAt":1619},"mcore-run-on-slurm","launch distributed training jobs on SLURM","How to launch distributed Megatron-LM training jobs on a SLURM cluster. Covers a minimal sbatch skeleton, environment-variable setup for torch.distributed.run, CUDA_DEVICE_MAX_CONNECTIONS rules across hardware and parallelism modes, container conventions, monitoring, and per-rank failure diagnosis.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1617,1618],{"name":1420,"slug":1421,"type":15},{"name":1423,"slug":1424,"type":15},"2026-07-14T05:25:49.362534",{"slug":1621,"name":1621,"fn":1622,"description":1623,"org":1624,"tags":1625,"stars":1533,"repoUrl":1534,"updatedAt":1633},"mcore-split-pr","split pull requests to reduce review load","Split a PR into multiple PRs to reduce the number of required CODEOWNERS reviewer groups.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1626,1629,1630],{"name":1627,"slug":1628,"type":15},"Code Review","code-review",{"name":1556,"slug":1557,"type":15},{"name":1631,"slug":1632,"type":15},"Pull Requests","pull-requests","2026-07-14T05:26:01.226578",{"slug":1635,"name":1635,"fn":1636,"description":1637,"org":1638,"tags":1639,"stars":1533,"repoUrl":1534,"updatedAt":1642},"mcore-testing","run and manage Megatron-LM tests","Test system for Megatron-LM. Covers test layout, recipe YAML structure, adding and running unit and functional tests, golden values, marker filters, and CI parity.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1640,1641],{"name":1607,"slug":1608,"type":15},{"name":1450,"slug":1451,"type":15},"2026-07-14T05:25:54.928983",{"slug":1644,"name":1644,"fn":1645,"description":1646,"org":1647,"tags":1648,"stars":1533,"repoUrl":1534,"updatedAt":1651},"nightly-sync","manage nightly main-to-dev sync workflows","Domain knowledge for the nightly main-to-dev sync workflow. Covers merge strategy, CI architecture, failure investigation, and known issues.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1649,1650],{"name":1460,"slug":1461,"type":15},{"name":1543,"slug":1544,"type":15},"2026-07-30T05:29:03.275638",496]