[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill-nvidia-jetson-customize-clocks":3,"mdc--ngu807-key":31,"related-repo-nvidia-jetson-customize-clocks":2668,"related-org-nvidia-jetson-customize-clocks":2772},{"slug":4,"name":4,"fn":5,"description":6,"org":7,"tags":11,"stars":20,"repoUrl":21,"updatedAt":22,"license":23,"forks":24,"topics":25,"repo":26,"sourceUrl":29,"mdContent":30},"jetson-customize-clocks","configure Jetson hardware clock settings","Use to lock\u002Fcap Jetson CPU\u002FGPU\u002FEMC clocks, toggle EMC\u002FCPU DVFS, or change cpufreq governors by editing BPMP DTB and nvpower.sh pre-flash. Do NOT use for live tuning or nvpmodel edits.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},"nvidia","NVIDIA","https:\u002F\u002Fpexgzepcugksgbtrxkhf.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Forg-logos\u002Fnvidia.png",[12,16,19],{"name":13,"slug":14,"type":15},"Performance","performance","tag",{"name":17,"slug":18,"type":15},"Hardware","hardware",{"name":9,"slug":8,"type":15},2473,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills","2026-07-14T05:29:59.370337","Apache-2.0",281,[],{"repoUrl":21,"stars":20,"forks":24,"topics":27,"description":28},[],"AI agent skills published by NVIDIA","https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills\u002Ftree\u002FHEAD\u002Fskills\u002Fjetson-customize-clocks","---\nname: jetson-customize-clocks\ndescription: Use to lock\u002Fcap Jetson CPU\u002FGPU\u002FEMC clocks, toggle EMC\u002FCPU DVFS, or change cpufreq governors by editing BPMP DTB and nvpower.sh pre-flash. Do NOT use for live tuning or nvpmodel edits.\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - clocks\n    - cpu\n    - gpu\n    - emc\n    - dvfs\n    - bwmgr\n    - bpmp\n    - nvpower\n    - cpufreq\n    - devfreq\n  domain: clocks\n---\n\n# Customize Clocks\n\n## Purpose\n\nCustomize CPU, GPU, and EMC clock behavior on a Jetson target by editing files under `Linux_for_Tegra\u002F` before flashing the image. Two layers are in scope:\n\n- The **BPMP DTB** at `Linux_for_Tegra\u002Fbootloader\u002F\u003CBPFDTB_FILE>` — per-clock `max-rate-custom` ceilings, plus the EMC DVFS gate (bwmgr + cactmon on all SoCs; osp-controller on T26x only).\n- **nvpower.sh** at `Linux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh` — cpufreq \u002F devfreq governors and (optionally) per-device min \u002F max \u002F static rates written to sysfs at boot.\n\nCommon triggers: \"lock CPU\u002FGPU\u002FEMC frequency\", \"pin GPU to Fmax\", \"pin EMC to MAXN\", \"disable\u002Fenable EMC DVFS\", \"disable\u002Fenable CPU DVFS\", \"set CPU\u002FGPU max rate\", \"change cpufreq governor\".\n\nOut of scope: runtime clock tuning on a live target (no flash step), nvpmodel power-mode edits (use the sibling skill `\u002Fjetson-customize-nvpmodel`), and silicon-ceiling overrides (`max-rate-maxn` is read-only).\n\n## Prerequisites\n\nResolve the active profile per\n[`..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md`](..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md).\nRefuse and route in these cases:\n\n| Condition | Refuse with |\n|---|---|\n| No active profile, or `active: NA` | Route to `\u002Fjetson-set-target` or `\u002Fjetson-init-target`. |\n| Profile lacks `bsp_image:` block | Route to `\u002Fjetson-init-image`. |\n| `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F` missing | Route to `\u002Fjetson-init-image`. |\n| `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` missing or not a git repo | Route to `\u002Fjetson-init-source`. |\n\nResolve paths:\n\n- `\u003Cbsp_image.root_path>` from `bsp_image.root_path:` if present, else `\u003Cworkspace>\u002FImage`.\n- `\u003Csource.root_path>` from `source.root_path:` if present, else `\u003Cworkspace>\u002FSource`.\n\n`\u003Cbsp_image.root_path>` is **read-only** for this skill; every write\n(Operation 1's BPMP DTB and Operation 2's `nvpower.sh`) lands under\n`\u003Csource.root_path>` (the overlay tracker). This is the workflow\ninvariant in\n[`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants`](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants) —\nhand-editing upstream silently destroys the diff trail and makes\n`\u002Fjetson-promote-image` a noop.\n\n## Instructions\n\n1. Resolve the prerequisites above (active profile, BSP image extracted, source overlay tracker initialized).\n2. Pick the operation from the table below.\n3. Follow the linked procedure section — Operation 1 (BPMP DTB), Operation 2 (`nvpower.sh`), or the MAXN recipe for both.\n4. Commit the edit inside the overlay tracker per each Operation's commit convention.\n5. Deploy with `\u002Fjetson-promote-image` → `\u002Fjetson-flash-image`. The new BPMP DTB and `nvpower.sh` take effect on the next boot.\n\n### Supported operations\n\n| Operation | Where the edit lives | Procedure section |\n|---|---|---|\n| Lock a CPU \u002F GPU clock to a specific rate | BPMP DTB `max-rate-custom` on the clock node + `nvpower.sh` governor `performance` | \"Content edit: `max-rate-custom`\" + \"Pick the edit\" |\n| Lock EMC at its init rate (disable EMC DVFS) | BPMP DTB: `bwmgr.enabled = 0`, `cactmon.enabled = 0`, plus `\u002Fdelete-node\u002F osp-controller` on T26x only | \"Content edit: EMC DVFS disable \u002F enable\" |\n| Re-enable EMC DVFS | BPMP DTB: `bwmgr.enabled = 1`, `cactmon.enabled = 1`, restore `osp-controller` on T26x | \"Content edit: EMC DVFS disable \u002F enable\" |\n| Pin everything to MAXN for stress runs | Combine the above + nvpmodel MAXN as boot default | see Recipe |\n| Lower a clock's hard ceiling without locking | BPMP DTB `max-rate-custom` only | \"Content edit: `max-rate-custom`\" |\n| Bound a device's rate without pinning | `nvpower.sh` min\u002Fmax via sysfs | \"Pick the edit\" |\n\n## Operation 1 — BPMP DTB edits\n\nFollow the BPMP-DTB customization protocol in\n[`..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md).\nThe protocol owns the mechanics — pristine import on first touch,\n`dtc` decompile, recompile, sanity-check, commit. This skill\nsupplies only the **clock-specific content** (which nodes and\nproperties to edit during the protocol's \"Edit the DTS\" step).\n\nThe edited `.dtb` lands in the `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F`\noverlay tracker. `\u002Fjetson-promote-image`'s channel A walks the\ntracker and copies the file into `bsp_image`. **Do not edit\n`\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F\u003Cbpmp-dtb>`\ndirectly** — that's the promote output, not an input.\n\n### Resolve the SKU-correct BPMP DTB\n\nPer the protocol's \"Resolving the active BPMP DTB\" section, read\n`BPFDTB_FILE` from the active flash conf. For the common Thor \u002F\nsingle-SKU conf shapes this is the static `BPFDTB_FILE=...` line\nin the per-board `.conf` and the value is authoritative as-is.\n\nFor **SKU-multiplexed conf shapes** (Orin AGX devkit conf chain\nthat selects a different BPMP DTB per `board_sku`\u002F`board_FAB`\nvia `update_flash_args_common` — see\n[`..\u002F..\u002Fcontext\u002Fbsp-customization-software-layers.md#per-board-conf-dispatch--update_flash_args_common`](..\u002F..\u002Fcontext\u002Fbsp-customization-software-layers.md#per-board-conf-dispatch--update_flash_args_common)),\nwalk the dispatch chain with `board_sku=\u003Cmodule.sku>` and\n`board_FAB=\u003Cmodule.revision or empty>` from the active profile,\nand read `BPFDTB_FILE` from the dispatch output — **not** from\nthe static line of the per-board `.conf`. Static and dispatched\nvalues match for non-multiplexed confs; the dispatch is\nmandatory only when the conf chain conditionally overrides\n`BPFDTB_FILE`.\n\n### List effective max rates (inspection)\n\nInspect both layers of the runtime ceiling — see [`references\u002Fclock-control-model.md#effective-runtime-ceiling`](references\u002Fclock-control-model.md#effective-runtime-ceiling) — before deciding on a `max-rate-custom` value.\n\nInspection cookbook (BPMP-side decompile + grep; nvpmodel-side awk over the boot default mode) is in [`references\u002Fbpmp-dtb-clock-edits.md#inspection-cookbook`](references\u002Fbpmp-dtb-clock-edits.md#inspection-cookbook).\n\nFor the nvpmodel layer see [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md).\n\nThis step does not mutate state — it's a precondition for sizing\nthe edit in the \"Content edit: `max-rate-custom` on a named clock node\" step.\n\n### Content edit: `max-rate-custom` on a named clock node\n\nDuring the \"Edit the DTS\" step of the protocol, modify the property\ninside the named clock node — never `lateinit`. `max-rate-custom`\nmust be strictly below the clock's hard cap (`max-rate-maxn` if\ndefined, otherwise the live `max_rate` from a running target of\nthe same chip \u002F SKU).\n\nDTS edit form, semantics, and the nvpmodel ↔ BPMP clock-node\nmapping live in [`references\u002Fbpmp-dtb-clock-edits.md`](references\u002Fbpmp-dtb-clock-edits.md).\n\nThen hand control back to the protocol — its \"Recompile\", \"Sanity-check\nthe recompiled blob\", \"Stage in the overlay tracker\", and \"Cleanup\"\nsteps cover the rest.\nCommit-message convention per the protocol:\n`\u003CBPMP_BASENAME>: jetson-customize-clocks — \u003Cclock-node> max-rate-custom = \u003Cvalue>`.\n\n### Content edit: EMC DVFS disable \u002F enable\n\nDefault behavior (EMC DVFS on) requires no edit. Disabling EMC\nDVFS is a **multi-node edit** applied inside the same \"Edit the DTS\" step of\nthe protocol, **not** a `bwmgr` toggle:\n\n| # | Edit | Scope |\n|---|---|---|\n| 1 | `bwmgr.enabled = \u003C0x00>` | All SoCs, mandatory |\n| 2 | `cactmon.enabled = \u003C0x00>` | All SoCs, mandatory |\n| 3 | `\u002Fdelete-node\u002F osp-controller` | **T26x (Thor) mandatory** — T23x (Orin) has no such node, skip |\n\nDetection: `dtc -I dtb -O dts \u003Cbpmp-dtb> | grep -c osp-controller`\n— zero hits ⇒ T23x path. Full DTS snippets, the surviving-paths\nfailure modes, and the re-enable procedure are in\n[`references\u002Femc-dvfs-disable.md`](references\u002Femc-dvfs-disable.md).\n\nApply the protocol's \"Recompile\" through \"Cleanup\" steps once the multi-node edit is in\nplace. Commit-message convention:\n`\u003CBPMP_BASENAME>: jetson-customize-clocks — EMC DVFS disable (bwmgr + cactmon[+ osp-controller])`.\n\nDisabling raises idle power; intended for stress \u002F performance\ntests, not production rootfs.\n\n### Re-run + idempotency\n\nPer the protocol's \"Re-runnability\" section, re-running this\nskill with the same target value produces a no-op commit. Re-\nrunning with a different value rewrites the same property — `git\nlog -- $BPMP_REL` shows the per-run history. To return a clock\nto its `max-rate-maxn` ceiling, edit the DTS to remove the\n`max-rate-custom` line and recompile.\n\n## Operation 2 — nvpower.sh edits\n\nEdits `nvpower.sh`, which runs at boot via `nvpower.service` to set\ncpufreq \u002F devfreq governors and rates.\n\n### The per-script file\n\nThe script this Operation edits has the relative path:\n\n```\nLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh\n```\n\nIt lives in **two** roots; the Operation walks both:\n\n| Role | Location | Skill writes? |\n|---|---|---|\n| Detection + pristine source | `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002F` | no — read-only |\n| Overlay edit target + git commit | `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002F` | yes |\n\nSubsequent sub-steps refer to **the per-script file** to mean the overlay\ncopy under `\u003Csource.root_path>`. The `\u003Cbsp_image.root_path>` copy is read\nonce during the pristine-import step below, then never touched again.\n\n### Overlay edit recipe (apply before editing nvpower.sh)\n\nFollow the canonical\n[Off-skill edits recipe](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#off-skill-edits)\nin the workflow doc — pristine import + customization commit pair, both\ngated by the preview gate. `nvpower.sh` is a single file with no\npropagation set; one pristine commit + one customization commit covers\nthe entire change.\n\nConcrete substitutions for this skill:\n\n- `\u003Crel>\u002F\u003Cfile>` is `rootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`.\n- Suggested pristine-import message:\n  `import pristine: rootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`,\n  body `Source: \u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F (BSP \u003Cbsp_image.version>)`.\n- Suggested customization-commit header:\n  `jetson-customize-clocks: nvpower.sh \u003Csummary>`,\n  body lines like `set_cpufreq_governor: desired_cpufreq_gov \"schedutil\" -> \"performance\"`.\n\n### Pick the edit\n\nFunction locations (`set_cpufreq_governor`, `set_devfreq_governor`), common-edit recipes (pin to Fmax, static rate, min\u002Fmax bounds), and the `nvidia-l4t-init` package-upgrade caveat live in [`references\u002Fnvpower-sh-edits.md`](references\u002Fnvpower-sh-edits.md).\n\n### Deploy\n\nThe customization commit in the overlay tracker does not reach the device\non its own. The Deploy chain:\n\n1. **`\u002Fjetson-promote-image`** — copies every tracked file in the overlay\n   into `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F`. Diff-aware (skip\n   byte-identical); uses `sudo cp -p` for `rootfs\u002F*` destinations.\n2. **`\u002Fjetson-flash-image`** — flashes the updated `bsp_image` to the\n   device. `nvpower.service` runs the new script on the next boot.\n3. (Alternate, no flash) Copy `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`\n   directly to the running target's `\u002Fetc\u002Fsystemd\u002Fnvpower.sh`, then\n   `sudo systemctl restart nvpower.service` (or reboot).\n\nEditing `\u003Csource.root_path>\u002F...` without committing — or editing\n`\u003Cbsp_image.root_path>\u002F...` directly — does nothing for `\u002Fjetson-promote-image`\nand is silently lost on the next `\u002Fjetson-init-image` re-extract.\n\n## Recipe — pin everything to MAXN for stress \u002F performance runs\n\nCombines Operations 1 + 2. Operation 1's BPMP edits all flow\nthrough one round of the protocol (a single decompile \u002F multi-node\nedit \u002F recompile \u002F commit cycle — don't round-trip the protocol\ntwice for the same `.dtb`):\n\n1. **BPMP DTB** (the \"Content edit: `max-rate-custom` on a named clock node\" step content): leave `max-rate-custom` unset on every CPU \u002F GPU \u002F EMC clock; remove existing `max-rate-custom` lines that lower the ceiling.\n2. **BPMP DTB** (the \"Content edit: EMC DVFS disable \u002F enable\" step content): pin EMC at its init rate — `bwmgr.enabled = 0`, `cactmon.enabled = 0`, plus `\u002Fdelete-node\u002F osp-controller` on T26x (skip on T23x).\n3. Apply both content edits inside one protocol \"Edit the DTS\" invocation, then run the remaining protocol steps (recompile, sanity-check, single customization commit covering both content edits).\n4. **nvpower.sh** (Operation 2): set `desired_cpufreq_gov=\"performance\"` and `desired_devfreq_gov=\"performance\"` unconditionally; remove the GPU\u002Fnvjpg skip in `set_devfreq_governor`. Applies via Operation 2's overlay edit recipe (the \"Overlay edit recipe (apply before editing nvpower.sh)\" step) — a separate overlay-tracker pristine + customization commit pair on the rootfs script, distinct from the BPMP-DTB protocol's commit.\n5. Set the boot-default nvpmodel mode to MAXN via [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md) — the per-clock nvpmodel cap clamps below `max-rate-maxn` regardless of BPMP DTB content.\n\nDeploy [`\u002Fjetson-promote-image`](..\u002Fjetson-promote-image\u002FSKILL.md) → [`\u002Fjetson-flash-image`](..\u002Fjetson-flash-image\u002FSKILL.md) picks up the new BPMP DTB (via the overlay tracker) and the edited `nvpower.sh` (via the same overlay tracker) on the next flash.\n\n## Limitations\n\n- **Image-build-time only.** All edits land under `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` and reach the device only via `\u002Fjetson-promote-image` → `\u002Fjetson-flash-image`. Live-target tuning is out of scope.\n- **`max-rate-custom` only lowers the ceiling.** It must be strictly below `max-rate-maxn`; raising the silicon cap is not supported.\n- **Effective ceiling is two-layer.** The runtime ceiling is `min(BPMP cap, active-nvpmodel-mode cap)`. The nvpmodel cap is owned by `\u002Fjetson-customize-nvpmodel`; this skill does not edit it.\n- **SoC-conditional EMC DVFS gate.** Disabling EMC DVFS requires editing different node sets on T23x (bwmgr + cactmon) vs T26x (bwmgr + cactmon + delete `osp-controller`). Mis-detection produces undefined behavior.\n- **T23x GPU cap is multi-node.** The GPU clock is split across `nafll_gpusys` and every `nafll_gpcX`; the cap binds only when applied to all of them.\n- **`nvpower.sh` is package-managed.** It ships in `nvidia-l4t-init`; package upgrades clobber in-place edits. Long-lived setups should prefer a systemd drop-in or sibling helper.\n- **ODMDATA wins.** When an ODMDATA token covers a property, the token overrides direct BPMP DTS edits at flash time. Direct BPMP DTS edits are the fallback for properties no NVIDIA token reaches.\n- **`max-rate-maxn` and `lateinit` are off-limits.** `max-rate-maxn` is the silicon ceiling (read-only). `lateinit` is for boot-time clock init, not ceiling overrides — never touch either.\n- **BPMP DTB may be SKU-multiplexed.** On compound \u002F dispatched flash confs (Orin AGX devkit chain), `BPFDTB_FILE` is selected by `board_sku` \u002F `board_FAB` via `update_flash_args_common`. Reading the static `BPFDTB_FILE=` line is wrong when the chain conditionally overrides it; resolve via the dispatch instead.\n\n## Troubleshooting\n\n| Error | Cause | Solution |\n|---|---|---|\n| `max-rate-custom` set but clock still ramps to `max-rate-maxn` on T23x GPU | Only `nafll_gpusys` was capped; the `nafll_gpcX` partitions still run at `max-rate-maxn` and dominate the effective ceiling. | Apply the same `max-rate-custom` to `nafll_gpusys` **and** every `nafll_gpcX` node enumerated by `grep -nE '^\\s*nafll_gpc[0-9]+\\s*:' \u003Cdecompiled.dts>`. |\n| EMC DVFS disable appears to apply but EMC still scales on T26x | Only `bwmgr.enabled = \u003C0x00>` was set; `osp-controller` survives and re-issues frequency changes via the QoS path. | Add edits #2 (`cactmon.enabled = \u003C0x00>`) and #3 (`\u002Fdelete-node\u002F osp-controller`) inside the same \"Edit the DTS\" step. Verify `osp-controller` via `dtc -I dtb -O dts \u003Cbpmp-dtb> \\| grep -c osp-controller` → expect 0. |\n| EMC DVFS disable rejected on T23x with \"node not found\" for `osp-controller` | T23x (Orin) BPMP DTBs do not contain `osp-controller`; edit #3 must be skipped on T23x. | Detect SoC family with the `grep -c osp-controller` step; only apply #3 when the count is ≥1. |\n| BPMP refuses to load DTB after edit: `max-rate-custom >= max-rate-maxn` | `max-rate-custom` was set to or above the silicon ceiling. | Lower `max-rate-custom` strictly below `max-rate-maxn`. If `max-rate-maxn` is absent from the node, query the live cap on a running target: `cat \u002Fsys\u002Fkernel\u002Fdebug\u002Fbpmp\u002Fdebug\u002Fclk\u002F\u003Cclock>\u002Fmax_rate`. |\n| `osp-controller` re-appears after `status = \"disabled\"` | `status = \"disabled\"` does not remove the node from the device tree; BPMP still walks it. | Replace with `\u002Fdelete-node\u002F osp-controller;` — the node must not exist for BPMP to skip the path. |\n| Edits to `nvpower.sh` lost after `apt upgrade` | `nvpower.sh` is owned by the `nvidia-l4t-init` deb and gets overwritten on upgrade. | For long-lived test setups, package edits into a systemd drop-in or a sibling helper file referenced by `nvpower.sh`, rather than editing `nvpower.sh` in place. |\n| `\u002Fjetson-promote-image` is a no-op after editing the BPMP DTB | The edit was applied to `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F`, which is `\u002Fjetson-promote-image`'s output — not its input. | Move the edit to `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F\u003CBPFDTB_FILE>` (the overlay tracker) and commit through the BPMP-DTB protocol. |\n| Cap appears to apply on first boot then resets after a power-mode change | The active nvpmodel mode's per-clock cap clamps below `max-rate-custom`. | Inspect both layers; if nvpmodel is binding, raise (or remove) the nvpmodel cap via `\u002Fjetson-customize-nvpmodel`. The BPMP cap alone is not the runtime ceiling. |\n\n## References\n\n- [`..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md) — canonical BPMP-DTB customization protocol (pristine import, decompile, edit, recompile, sanity-check, commit). Operation 1 of this skill is a content-only consumer; the protocol owns the mechanics.\n- [`references\u002Fclock-control-model.md`](references\u002Fclock-control-model.md) — layer stack, two-ceilings overview, effective-runtime-ceiling formula.\n- [`references\u002Fbpmp-dtb-clock-edits.md`](references\u002Fbpmp-dtb-clock-edits.md) — two-ceilings semantics, DTS edit form, nvpmodel ↔ BPMP clock-node mapping, inspection cookbook.\n- [`references\u002Femc-dvfs-disable.md`](references\u002Femc-dvfs-disable.md) — full SoC-conditional EMC DVFS disable procedure with DTS snippets, detection, re-enable.\n- [`references\u002Fnvpower-sh-edits.md`](references\u002Fnvpower-sh-edits.md) — `nvpower.sh` function locations + common-edit recipes + package-upgrade caveat.\n- [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md) — sibling skill: nvpmodel power modes. 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Use when users ask how to install, configure, operate, troubleshoot, secure, or learn NemoClaw with an AI coding assistant. Trigger keywords - nemoclaw docs, use nemoclaw with ai agent, nemoclaw mcp docs, nemoclaw install help, nemoclaw quickstart, nemoclaw markdown docs, llms.txt, agent skills.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2780,2783,2786],{"name":2781,"slug":2782,"type":15},"Documentation","documentation",{"name":2784,"slug":2785,"type":15},"MCP","mcp",{"name":2787,"slug":2788,"type":15},"Search","search",21777,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FNemoClaw","2026-07-20T06:00:01.461044",{"slug":2793,"name":2793,"fn":2794,"description":2795,"org":2796,"tags":2797,"stars":2805,"repoUrl":2806,"updatedAt":2807},"mcore-build-and-dependency","manage Megatron-LM development environments","Container-based dev environment setup and dependency management for Megatron-LM. Covers acquiring and launching the CI container, uv package management, and updating uv.lock.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2798,2801,2802],{"name":2799,"slug":2800,"type":15},"Containers","containers",{"name":2692,"slug":2693,"type":15},{"name":2803,"slug":2804,"type":15},"Python","python",17049,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FMegatron-LM","2026-07-27T06:06:11.249662",{"slug":2809,"name":2809,"fn":2810,"description":2811,"org":2812,"tags":2813,"stars":2805,"repoUrl":2806,"updatedAt":2818},"mcore-bump-base-image","update NVIDIA PyTorch base images","Bump the NVIDIA PyTorch base image (`nvcr.io\u002Fnvidia\u002Fpytorch:YY.MM-py3`) used by Megatron-LM CI. Covers the two pin sites (GitHub CI in `docker\u002F.ngc_version.dev` and GitLab CI in `.gitlab\u002Fstages\u002F01.build.yml`), the post-bump CI loop (re-run functional tests, refresh golden values, mark broken tests), and the gotchas that bit PRs",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2814,2817],{"name":2815,"slug":2816,"type":15},"CI\u002FCD","ci-cd",{"name":2692,"slug":2693,"type":15},"2026-07-14T05:25:59.97109",{"slug":2820,"name":2820,"fn":2821,"description":2822,"org":2823,"tags":2824,"stars":2805,"repoUrl":2806,"updatedAt":2830},"mcore-cicd","manage CI\u002FCD pipelines for Megatron-LM","CI\u002FCD reference for Megatron-LM. Covers CI pipeline structure, PR scope labels, triggering internal GitLab CI (which force-pushes the current branch to a pull-request\u002FBRANCH ref — always dry-run and verify the destination first; never run against shared or protected branches), and CI failure investigation.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2825,2826,2827],{"name":2815,"slug":2816,"type":15},{"name":2692,"slug":2693,"type":15},{"name":2828,"slug":2829,"type":15},"GitHub","github","2026-07-27T06:06:12.278222",{"slug":2832,"name":2832,"fn":2833,"description":2834,"org":2835,"tags":2836,"stars":2805,"repoUrl":2806,"updatedAt":2844},"mcore-create-issue","investigate CI failures and create issues","Investigate a failing GitHub Actions run or job and create a GitHub issue for the failure.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2837,2840,2841],{"name":2838,"slug":2839,"type":15},"Debugging","debugging",{"name":2828,"slug":2829,"type":15},{"name":2842,"slug":2843,"type":15},"Triage","triage","2026-07-14T05:25:57.442089",{"slug":2846,"name":2846,"fn":2847,"description":2848,"org":2849,"tags":2850,"stars":2805,"repoUrl":2806,"updatedAt":2857},"mcore-linting-and-formatting","lint and format Megatron-LM code","Linting and formatting for Megatron-LM. Covers running autoformat.sh, tools (ruff, black, isort, pylint, mypy), and code style rules.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2851,2854],{"name":2852,"slug":2853,"type":15},"Best Practices","best-practices",{"name":2855,"slug":2856,"type":15},"Code Analysis","code-analysis","2026-07-14T05:25:56.18433",{"slug":2859,"name":2859,"fn":2860,"description":2861,"org":2862,"tags":2863,"stars":2805,"repoUrl":2806,"updatedAt":2871},"mcore-migrate-gpt-to-hybrid","migrate Megatron-LM models to HybridModel","Migration guide for moving Megatron Core GPTModel checkpoints, model providers, training commands, and layer mappings to HybridModel.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2864,2867,2870],{"name":2865,"slug":2866,"type":15},"Machine Learning","machine-learning",{"name":2868,"slug":2869,"type":15},"Migration","migration",{"name":9,"slug":8,"type":15},"2026-07-17T06:07:11.777011",{"slug":2873,"name":2873,"fn":2874,"description":2875,"org":2876,"tags":2877,"stars":2805,"repoUrl":2806,"updatedAt":2882},"mcore-onboard-gb200-1node-tests","onboard functional tests for GB200","Onboard 1-node GitHub MR functional tests for GB200 from existing mr-scoped 2-node tests.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2878,2881],{"name":2879,"slug":2880,"type":15},"QA","qa",{"name":2722,"slug":2723,"type":15},"2026-07-14T05:25:53.673039",{"slug":2884,"name":2884,"fn":2885,"description":2886,"org":2887,"tags":2888,"stars":2805,"repoUrl":2806,"updatedAt":2891},"mcore-run-on-slurm","launch distributed training jobs on SLURM","How to launch distributed Megatron-LM training jobs on a SLURM cluster. Covers a minimal sbatch skeleton, environment-variable setup for torch.distributed.run, CUDA_DEVICE_MAX_CONNECTIONS rules across hardware and parallelism modes, container conventions, monitoring, and per-rank failure diagnosis.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2889,2890],{"name":2692,"slug":2693,"type":15},{"name":2695,"slug":2696,"type":15},"2026-07-14T05:25:49.362534",{"slug":2893,"name":2893,"fn":2894,"description":2895,"org":2896,"tags":2897,"stars":2805,"repoUrl":2806,"updatedAt":2905},"mcore-split-pr","split pull requests to reduce review load","Split a PR into multiple PRs to reduce the number of required CODEOWNERS reviewer groups.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2898,2901,2902],{"name":2899,"slug":2900,"type":15},"Code Review","code-review",{"name":2828,"slug":2829,"type":15},{"name":2903,"slug":2904,"type":15},"Pull Requests","pull-requests","2026-07-14T05:26:01.226578",{"slug":2907,"name":2907,"fn":2908,"description":2909,"org":2910,"tags":2911,"stars":2805,"repoUrl":2806,"updatedAt":2914},"mcore-testing","run and manage Megatron-LM tests","Test system for Megatron-LM. Covers test layout, recipe YAML structure, adding and running unit and functional tests, golden values, marker filters, and CI parity.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2912,2913],{"name":2879,"slug":2880,"type":15},{"name":2722,"slug":2723,"type":15},"2026-07-14T05:25:54.928983",{"slug":2916,"name":2916,"fn":2917,"description":2918,"org":2919,"tags":2920,"stars":2805,"repoUrl":2806,"updatedAt":2923},"nightly-sync","manage nightly main-to-dev sync workflows","Domain knowledge for the nightly main-to-dev sync workflow. Covers merge strategy, CI architecture, failure investigation, and known issues.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[2921,2922],{"name":2732,"slug":2733,"type":15},{"name":2815,"slug":2816,"type":15},"2026-07-30T05:29:03.275638",496]