[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill-nvidia-hsb-ip-create-top":3,"mdc--8jv36k-key":31,"related-repo-nvidia-hsb-ip-create-top":1130,"related-org-nvidia-hsb-ip-create-top":1236},{"slug":4,"name":4,"fn":5,"description":6,"org":7,"tags":11,"stars":20,"repoUrl":21,"updatedAt":22,"license":23,"forks":24,"topics":25,"repo":26,"sourceUrl":29,"mdContent":30},"hsb-ip-create-top","create HSB FPGA top wrappers","Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},"nvidia","NVIDIA","https:\u002F\u002Fpexgzepcugksgbtrxkhf.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Forg-logos\u002Fnvidia.png",[12,16,17],{"name":13,"slug":14,"type":15},"Hardware","hardware","tag",{"name":9,"slug":8,"type":15},{"name":18,"slug":19,"type":15},"Engineering","engineering",2473,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills","2026-08-05T05:58:12.109672","Apache-2.0",281,[],{"repoUrl":21,"stars":20,"forks":24,"topics":27,"description":28},[],"AI agent skills published by NVIDIA","https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fskills\u002Ftree\u002FHEAD\u002Fskills\u002Fhsb-ip-create-top","---\nname: hsb-ip-create-top\nauthor: \"Holoscan Team \u003Choloscan-team@nvidia.com>\"\ndescription: Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.\nversion: \"0.1.0\"\ntags:\n  - holoscan\n  - hsb\n  - fpga\n  - systemverilog\n  - top-level\nlicense: Apache-2.0\ncompatibility: Targets HSB IP rev 16'h2604; backward-compatible with 16'h2603. Prefer live HSB IP source when available; warn on unknown revisions. Designed to work standalone or as a companion to hsb-ip-def.\nmetadata:\n  author: \"Holoscan Team \u003Choloscan-team@nvidia.com>\"\n  team: holoscan\n  domain: fpga\n  vendor: nvidia\n  tags:\n    - holoscan\n    - hsb\n    - fpga\n    - top-level\n    - systemverilog\n  languages:\n    - systemverilog\n  artifact: FPGA_top.sv\n  source_artifact: HOLOLINK_def.svh\n  hsb_ip_version: \"16'h2604\"\n---\n\n# HSB IP Create Top Skill\n\n## Purpose\n\nCreate a fixed-format SystemVerilog top-level scaffold that instantiates `HOLOLINK_top` and declares the HSB-facing signals required by a validated `HOLOLINK_def.svh`.\n\nThis skill owns only the top-level scaffold around the HSB IP:\n\n- SPDX\u002FApache license header\n- `HOLOLINK_def.svh` include\n- `FPGA_top` module shell\n- HSB-facing signal declarations\n- `HOLOLINK_top` instantiation\n- comments\u002FTODOs for top-level integration\n\nUse `hsb-ip-def` for `HOLOLINK_def.svh` generation and validation. Do not create or validate the defs file here.\n\n## Prerequisites\n\n- A validated `HOLOLINK_def.svh` path or pasted file content is required before generating `FPGA_top.sv`.\n- Live `HOLOLINK_top.sv` source is preferred when source-sensitive port extraction is needed; bundled references cover known rev `16'h2604` and compatible rev `16'h2603`.\n- The user must provide or accept the output path when writing a scaffold file.\n\n## Instructions\n\n- Require a validated `HOLOLINK_def.svh` before creating `FPGA_top.sv`. If the user does not have one, invoke or direct them to `hsb-ip-def` first.\n- Treat live `HOLOLINK_top.sv` as the source of truth for ports, directions, macro gates, and IP revision whenever it is available.\n- First classify the request as Standalone Create Top, Def-Skill Handoff, or Explain. Load only the references required for that workflow and do not re-read the same reference just to reconfirm formatting.\n- Use `references\u002Ffixed-format.md` as the baked formatting and naming style. Do not inspect example top-level files just to confirm formatting during normal generation.\n- Emit a fixed-format scaffold, not a complete project top. Because the surrounding design is unknown, the generated `FPGA_top` module normally has no top-level ports.\n- Derive active signal groups from the validated defs file. Do not connect ports that are absent from `HOLOLINK_top` under the active macro set.\n- Preserve `HOLOLINK_top` port shapes exactly: keep packed vector widths before the signal name and unpacked interface-array dimensions after the signal name.\n- When using bundled known-rev references, still preserve the signal shapes in `references\u002Ffixed-format.md`, including unpacked arrays for multi-interface `*_tdata`, `*_tkeep`, and `*_tuser` buses and the APB shape documented there.\n- Use sensor-agnostic language. Say \"sensor data\", \"sensor interface\", and \"stream\"; use camera-specific language only after the user says the design is camera-specific.\n- Ask one plain-language question per turn when information is missing. Keep source-selection questions as plain-language prompts rather than radio buttons, structured choices, or multi-question prompts.\n- Do not invent project-specific integration details. Leave concise TODO comments where the surrounding design must connect to HSB.\n- For packetizer comments in `FPGA_top.sv`, use generic wording such as \"data manipulation behavior\".\n- In final summaries, include the defs validation\u002Fsource status, the port-map source used, and the emitted HSB signal groups. Do not enumerate what is outside the scaffold's scope. Use only this generic note: \"This file is a reference\u002Ftemplate for hooking up top-level signals and companion IP to the HSB IP.\"\n\n## Live HSB IP Source Policy\n\nPrefer live HSB IP source over bundled references whenever the user's workspace provides it. The bundled references describe known rev `16'h2604` and backward-compatible rev `16'h2603`; live source is the authority for the checked-out IP.\n\nWhen source is available:\n\n1. Locate `\u003Chsb-ip-root>\u002Ftop\u002FHOLOLINK_top.sv`. Known roots include `hw\u002Fnvcpu_dgx_fpga\u002Fvrtl\u002Fhololink\u002F` and public-release `fpga\u002Fnv_hsb_ip\u002F`.\n2. Read `HOLOLINK_REV` and `HOLOLINK_BACKWARD_COMPAT_REV` from `HOLOLINK_top.sv`.\n3. Read the `HOLOLINK_top` module declaration to confirm port names, directions, widths, ordering, and `ifdef`\u002F`ifndef` gates.\n4. If the rev is newer, unknown, or the live source disagrees with this skill's references, state the mismatch. Trust the live source for IO extraction and warn that bundled references may need an update.\n\nWhen no source is available, use the bundled references as known-revision guidance and say the scaffold is based on the skill's supported HSB IP rev. If the user already authorized using the bundled known-rev port reference when no checkout is obvious, do a brief search of obvious roots and then proceed with bundled references instead of asking the live-source question.\n\nIf the source root is not obvious, ask conversationally in one turn:\n\n```text\nDo you have a current HSB IP `HOLOLINK_top.sv` source checkout you want me to use for port extraction, or should I use the skill's bundled known-rev port reference?\n```\n\nAccept either a path or a \"use bundled reference\" answer.\n\n## Reference Loading\n\nLoad only the reference needed for the user's task:\n\n| File | When to load |\n|---|---|\n| `references\u002Fsource-policy.md` | Finding live HSB IP source, handling unknown revisions, or deciding source\u002Freference precedence |\n| `references\u002Ffixed-format.md` | Generating or explaining the fixed `FPGA_top.sv` scaffold format |\n| `references\u002Fhandoff-contract.md` | Standalone prerequisite handling or def-skill handoff behavior |\n\n## Workflow Decision\n\n1. If invoked by `hsb-ip-def` after a successful defs generation\u002Fvalidation, use **Def-Skill Handoff**.\n2. If the user directly asks to create `FPGA_top.sv`, instantiate `HOLOLINK_top`, or make a top-level wrapper, use **Standalone Create Top**.\n3. If the user asks about version handling, port groups, or why a signal appears, use **Explain**.\n\n## Standalone Create Top\n\nUse this when the user invokes this skill directly.\n\nSteps:\n\n1. Ask for the path to a validated `HOLOLINK_def.svh`, or accept pasted content. If the user does not have a defs file, stop and direct them to `hsb-ip-def` to create and validate it first.\n2. If validation status is unknown, invoke or direct the user to `hsb-ip-def` validation. Do not proceed from an unvalidated defs file.\n3. If the HSB IP source root is not obvious and source-sensitive output is needed, ask the live-source question from \"Live HSB IP Source Policy\" unless the user already authorized bundled known-rev fallback. Do not show path options as radio buttons. The known roots are search hints for the agent, not choices to force on the user.\n4. Load `references\u002Fsource-policy.md` and `references\u002Ffixed-format.md`.\n5. Derive the active macro set from the validated defs file.\n6. Derive or verify `HOLOLINK_top` port groups from live source when available.\n7. Produce `FPGA_top.sv` in the fixed format. If writing a file, default filename is `FPGA_top.sv` unless the user provides a path.\n8. Explain that the result is an HSB integration scaffold. Use the generic reference\u002Ftemplate note in `## Instructions`; do not enumerate what is outside the scaffold's scope.\n\n## Def-Skill Handoff\n\nUse this when `hsb-ip-def` has just completed a validated `HOLOLINK_def.svh` and the user chooses to create a matching top-level scaffold.\n\nSteps:\n\n1. Accept the validated defs file path\u002Fcontent and any known profile\u002Fsource-root context from `hsb-ip-def`.\n2. Do not re-ask for defs-file decisions already completed by the def skill.\n3. Ask only for missing top-generation facts, such as output path or HSB IP source root when needed. If source root is missing, ask the live-source question from \"Live HSB IP Source Policy\" unless the user already authorized bundled known-rev fallback; do not use radio buttons or structured choices.\n4. Load `references\u002Fhandoff-contract.md` and `references\u002Ffixed-format.md`.\n5. Generate the fixed-format `FPGA_top.sv` scaffold from the active defs macros and live `HOLOLINK_top.sv` when available.\n6. Return a concise summary of which HSB signal groups were emitted, then use the generic reference\u002Ftemplate note in `## Instructions`. Do not enumerate what is outside the scaffold's scope.\n\n## Explain\n\nUse this when the user asks why a port or signal group appears, how macro settings affect the top scaffold, or how the skill handles IP revisions.\n\nSteps:\n\n1. For port questions, prefer live `HOLOLINK_top.sv` when available. Otherwise load `references\u002Ffixed-format.md`.\n2. For revision\u002Fsource questions, load `references\u002Fsource-policy.md`.\n3. For defs-file macro meaning, defer to `hsb-ip-def`.\n\n## Troubleshooting\n\n- Missing or unvalidated defs file: stop before generation and send the user to `hsb-ip-def` validation.\n- Unknown or newer HSB IP revision: prefer live source if available, state the mismatch, and warn that bundled references may need updates.\n- Port missing under the active macro set: omit that connection and explain which validated def macro disabled the signal group.\n\n## Examples\n\n- `Use hsb-ip-create-top to create an FPGA_top.sv scaffold from my validated HOLOLINK_def.svh. Use the bundled known-rev port reference if no HSB IP source checkout is obvious.` Treat as Standalone Create Top, require the validated defs file, load `references\u002Fsource-policy.md` and `references\u002Ffixed-format.md`, use bundled known-rev ports after a brief source search, and report the defs status, port-map source, and emitted signal groups.\n- `Create a top-level FPGA_top.sv wrapper for HSB, but I do not have a HOLOLINK_def.svh yet.` Stop before generation, direct the user to `hsb-ip-def`, and ask for a validated defs file path or content before proceeding.\n- `Why does the generated FPGA_top.sv include different HSB signal groups depending on my HOLOLINK_def.svh macros?` Treat as Explain, say that validated defs macros gate the HSB-facing signal groups and that the live `HOLOLINK_top.sv` port map wins when available; defer detailed macro semantics to `hsb-ip-def`.\n\n## Limitations\n\n- Do not generate `HOLOLINK_def.svh`.\n- Do not validate full `HOLOLINK_def.svh` files.\n- Do not generate project-specific integration outside the HSB-facing scaffold.\n- Do not infer signal meanings, polarity, sources, or behavior outside the HSB port map.\n- Do not copy example project logic into the scaffold unless the user explicitly requests project-specific adaptation.\n",{"data":32,"body":48},{"name":4,"author":33,"description":6,"version":34,"tags":35,"license":23,"compatibility":41,"metadata":42},"Holoscan Team \u003Choloscan-team@nvidia.com>","0.1.0",[36,37,38,39,40],"holoscan","hsb","fpga","systemverilog","top-level","Targets HSB IP rev 16'h2604; backward-compatible with 16'h2603. Prefer live HSB IP source when available; warn on unknown revisions. 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Load only the references required for that workflow and do not re-read the same reference just to reconfirm formatting.",{"type":52,"tag":99,"props":277,"children":278},{},[279,280,286],{"type":58,"value":149},{"type":52,"tag":74,"props":281,"children":283},{"className":282},[],[284],{"type":58,"value":285},"references\u002Ffixed-format.md",{"type":58,"value":287}," as the baked formatting and naming style. Do not inspect example top-level files just to confirm formatting during normal generation.",{"type":52,"tag":99,"props":289,"children":290},{},[291,293,298],{"type":58,"value":292},"Emit a fixed-format scaffold, not a complete project top. Because the surrounding design is unknown, the generated ",{"type":52,"tag":74,"props":294,"children":296},{"className":295},[],[297],{"type":58,"value":122},{"type":58,"value":299}," module normally has no top-level ports.",{"type":52,"tag":99,"props":301,"children":302},{},[303,305,310],{"type":58,"value":304},"Derive active signal groups from the validated defs file. Do not connect ports that are absent from ",{"type":52,"tag":74,"props":306,"children":308},{"className":307},[],[309],{"type":58,"value":79},{"type":58,"value":311}," under the active macro set.",{"type":52,"tag":99,"props":313,"children":314},{},[315,317,322],{"type":58,"value":316},"Preserve ",{"type":52,"tag":74,"props":318,"children":320},{"className":319},[],[321],{"type":58,"value":79},{"type":58,"value":323}," port shapes exactly: keep packed vector widths before the signal name and unpacked interface-array dimensions after the signal name.",{"type":52,"tag":99,"props":325,"children":326},{},[327,329,334,336,342,344,350,352,358],{"type":58,"value":328},"When using bundled known-rev references, still preserve the signal shapes in ",{"type":52,"tag":74,"props":330,"children":332},{"className":331},[],[333],{"type":58,"value":285},{"type":58,"value":335},", including unpacked arrays for multi-interface ",{"type":52,"tag":74,"props":337,"children":339},{"className":338},[],[340],{"type":58,"value":341},"*_tdata",{"type":58,"value":343},", ",{"type":52,"tag":74,"props":345,"children":347},{"className":346},[],[348],{"type":58,"value":349},"*_tkeep",{"type":58,"value":351},", and ",{"type":52,"tag":74,"props":353,"children":355},{"className":354},[],[356],{"type":58,"value":357},"*_tuser",{"type":58,"value":359}," buses and the APB shape documented there.",{"type":52,"tag":99,"props":361,"children":362},{},[363],{"type":58,"value":364},"Use sensor-agnostic language. Say \"sensor data\", \"sensor interface\", and \"stream\"; use camera-specific language only after the user says the design is camera-specific.",{"type":52,"tag":99,"props":366,"children":367},{},[368],{"type":58,"value":369},"Ask one plain-language question per turn when information is missing. Keep source-selection questions as plain-language prompts rather than radio buttons, structured choices, or multi-question prompts.",{"type":52,"tag":99,"props":371,"children":372},{},[373],{"type":58,"value":374},"Do not invent project-specific integration details. Leave concise TODO comments where the surrounding design must connect to HSB.",{"type":52,"tag":99,"props":376,"children":377},{},[378,380,385],{"type":58,"value":379},"For packetizer comments in ",{"type":52,"tag":74,"props":381,"children":383},{"className":382},[],[384],{"type":58,"value":45},{"type":58,"value":386},", use generic wording such as \"data manipulation behavior\".",{"type":52,"tag":99,"props":388,"children":389},{},[390],{"type":58,"value":391},"In final summaries, include the defs validation\u002Fsource status, the port-map source used, and the emitted HSB signal groups. Do not enumerate what is outside the scaffold's scope. Use only this generic note: \"This file is a reference\u002Ftemplate for hooking up top-level signals and companion IP to the HSB IP.\"",{"type":52,"tag":61,"props":393,"children":395},{"id":394},"live-hsb-ip-source-policy",[396],{"type":58,"value":397},"Live HSB IP Source Policy",{"type":52,"tag":68,"props":399,"children":400},{},[401,403,408,410,415],{"type":58,"value":402},"Prefer live HSB IP source over bundled references whenever the user's workspace provides it. The bundled references describe known rev ",{"type":52,"tag":74,"props":404,"children":406},{"className":405},[],[407],{"type":58,"value":47},{"type":58,"value":409}," and backward-compatible rev ",{"type":52,"tag":74,"props":411,"children":413},{"className":412},[],[414],{"type":58,"value":217},{"type":58,"value":416},"; live source is the authority for the checked-out IP.",{"type":52,"tag":68,"props":418,"children":419},{},[420],{"type":58,"value":421},"When source is available:",{"type":52,"tag":423,"props":424,"children":425},"ol",{},[426,454,481,509],{"type":52,"tag":99,"props":427,"children":428},{},[429,431,437,439,445,447,453],{"type":58,"value":430},"Locate ",{"type":52,"tag":74,"props":432,"children":434},{"className":433},[],[435],{"type":58,"value":436},"\u003Chsb-ip-root>\u002Ftop\u002FHOLOLINK_top.sv",{"type":58,"value":438},". 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For RTSP\u002Flive streams, use amc-run-rtsp-calibration instead.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1195,1198,1201,1202],{"name":1196,"slug":1197,"type":15},"Automation","automation",{"name":1199,"slug":1200,"type":15},"Imaging","imaging",{"name":9,"slug":8,"type":15},{"name":1203,"slug":1204,"type":15},"Video","video","2026-07-17T05:28:53.905004",{"slug":1207,"name":1207,"fn":1208,"description":1209,"org":1210,"tags":1211,"stars":20,"repoUrl":21,"updatedAt":1220},"amc-setup-calibration-stack","deploy AutoMagicCalib microservice with Docker","Launch AutoMagicCalib microservice and web UI from NGC release images via Docker Compose. Use when user says 'deploy auto calibration', 'launch auto calibration', 'launch AMC', 'start MS+UI', or 'set up auto-magic-calib'. Requires NGC API key.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1212,1213,1216,1217],{"name":1156,"slug":1157,"type":15},{"name":1214,"slug":1215,"type":15},"Docker","docker",{"name":9,"slug":8,"type":15},{"name":1218,"slug":1219,"type":15},"Operations","operations","2026-07-17T05:28:56.913999",{"slug":1222,"name":1222,"fn":1223,"description":1224,"org":1225,"tags":1226,"stars":20,"repoUrl":21,"updatedAt":1234},"cudaq-guide","develop quantum applications with CUDA-Q","CUDA-Q onboarding guide for installation, test programs, GPU simulation, QPU hardware, and quantum applications.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1227,1228,1231],{"name":9,"slug":8,"type":15},{"name":1229,"slug":1230,"type":15},"Quantum Computing","quantum-computing",{"name":1232,"slug":1233,"type":15},"Simulation","simulation","2026-07-14T05:26:58.898253",310,{"items":1237,"total":1388},[1238,1256,1272,1283,1295,1309,1322,1336,1347,1356,1370,1379],{"slug":1239,"name":1239,"fn":1240,"description":1241,"org":1242,"tags":1243,"stars":1253,"repoUrl":1254,"updatedAt":1255},"nemoclaw-user-guide","retrieve NemoClaw documentation and configuration","Guides human users' AI agents to the NemoClaw docs MCP server and canonical Fern documentation in Markdown form. Use when users ask how to install, configure, operate, troubleshoot, secure, or learn NemoClaw with an AI coding assistant. Trigger keywords - nemoclaw docs, use nemoclaw with ai agent, nemoclaw mcp docs, nemoclaw install help, nemoclaw quickstart, nemoclaw markdown docs, llms.txt, agent skills.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1244,1247,1250],{"name":1245,"slug":1246,"type":15},"Documentation","documentation",{"name":1248,"slug":1249,"type":15},"MCP","mcp",{"name":1251,"slug":1252,"type":15},"Search","search",21777,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FNemoClaw","2026-07-20T06:00:01.461044",{"slug":1257,"name":1257,"fn":1258,"description":1259,"org":1260,"tags":1261,"stars":1269,"repoUrl":1270,"updatedAt":1271},"mcore-build-and-dependency","manage Megatron-LM development environments","Container-based dev environment setup and dependency management for Megatron-LM. Covers acquiring and launching the CI container, uv package management, and updating uv.lock.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1262,1265,1266],{"name":1263,"slug":1264,"type":15},"Containers","containers",{"name":1156,"slug":1157,"type":15},{"name":1267,"slug":1268,"type":15},"Python","python",17049,"https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FMegatron-LM","2026-07-27T06:06:11.249662",{"slug":1273,"name":1273,"fn":1274,"description":1275,"org":1276,"tags":1277,"stars":1269,"repoUrl":1270,"updatedAt":1282},"mcore-bump-base-image","update NVIDIA PyTorch base images","Bump the NVIDIA PyTorch base image (`nvcr.io\u002Fnvidia\u002Fpytorch:YY.MM-py3`) used by Megatron-LM CI. Covers the two pin sites (GitHub CI in `docker\u002F.ngc_version.dev` and GitLab CI in `.gitlab\u002Fstages\u002F01.build.yml`), the post-bump CI loop (re-run functional tests, refresh golden values, mark broken tests), and the gotchas that bit PRs",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1278,1281],{"name":1279,"slug":1280,"type":15},"CI\u002FCD","ci-cd",{"name":1156,"slug":1157,"type":15},"2026-07-14T05:25:59.97109",{"slug":1284,"name":1284,"fn":1285,"description":1286,"org":1287,"tags":1288,"stars":1269,"repoUrl":1270,"updatedAt":1294},"mcore-cicd","manage CI\u002FCD pipelines for Megatron-LM","CI\u002FCD reference for Megatron-LM. Covers CI pipeline structure, PR scope labels, triggering internal GitLab CI (which force-pushes the current branch to a pull-request\u002FBRANCH ref — always dry-run and verify the destination first; never run against shared or protected branches), and CI failure investigation.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1289,1290,1291],{"name":1279,"slug":1280,"type":15},{"name":1156,"slug":1157,"type":15},{"name":1292,"slug":1293,"type":15},"GitHub","github","2026-07-27T06:06:12.278222",{"slug":1296,"name":1296,"fn":1297,"description":1298,"org":1299,"tags":1300,"stars":1269,"repoUrl":1270,"updatedAt":1308},"mcore-create-issue","investigate CI failures and create issues","Investigate a failing GitHub Actions run or job and create a GitHub issue for the failure.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1301,1304,1305],{"name":1302,"slug":1303,"type":15},"Debugging","debugging",{"name":1292,"slug":1293,"type":15},{"name":1306,"slug":1307,"type":15},"Triage","triage","2026-07-14T05:25:57.442089",{"slug":1310,"name":1310,"fn":1311,"description":1312,"org":1313,"tags":1314,"stars":1269,"repoUrl":1270,"updatedAt":1321},"mcore-linting-and-formatting","lint and format Megatron-LM code","Linting and formatting for Megatron-LM. Covers running autoformat.sh, tools (ruff, black, isort, pylint, mypy), and code style rules.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1315,1318],{"name":1316,"slug":1317,"type":15},"Best Practices","best-practices",{"name":1319,"slug":1320,"type":15},"Code Analysis","code-analysis","2026-07-14T05:25:56.18433",{"slug":1323,"name":1323,"fn":1324,"description":1325,"org":1326,"tags":1327,"stars":1269,"repoUrl":1270,"updatedAt":1335},"mcore-migrate-gpt-to-hybrid","migrate Megatron-LM models to HybridModel","Migration guide for moving Megatron Core GPTModel checkpoints, model providers, training commands, and layer mappings to HybridModel.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1328,1331,1334],{"name":1329,"slug":1330,"type":15},"Machine Learning","machine-learning",{"name":1332,"slug":1333,"type":15},"Migration","migration",{"name":9,"slug":8,"type":15},"2026-07-17T06:07:11.777011",{"slug":1337,"name":1337,"fn":1338,"description":1339,"org":1340,"tags":1341,"stars":1269,"repoUrl":1270,"updatedAt":1346},"mcore-onboard-gb200-1node-tests","onboard functional tests for GB200","Onboard 1-node GitHub MR functional tests for GB200 from existing mr-scoped 2-node tests.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1342,1345],{"name":1343,"slug":1344,"type":15},"QA","qa",{"name":1186,"slug":1187,"type":15},"2026-07-14T05:25:53.673039",{"slug":1348,"name":1348,"fn":1349,"description":1350,"org":1351,"tags":1352,"stars":1269,"repoUrl":1270,"updatedAt":1355},"mcore-run-on-slurm","launch distributed training jobs on SLURM","How to launch distributed Megatron-LM training jobs on a SLURM cluster. Covers a minimal sbatch skeleton, environment-variable setup for torch.distributed.run, CUDA_DEVICE_MAX_CONNECTIONS rules across hardware and parallelism modes, container conventions, monitoring, and per-rank failure diagnosis.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1353,1354],{"name":1156,"slug":1157,"type":15},{"name":1159,"slug":1160,"type":15},"2026-07-14T05:25:49.362534",{"slug":1357,"name":1357,"fn":1358,"description":1359,"org":1360,"tags":1361,"stars":1269,"repoUrl":1270,"updatedAt":1369},"mcore-split-pr","split pull requests to reduce review load","Split a PR into multiple PRs to reduce the number of required CODEOWNERS reviewer groups.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1362,1365,1366],{"name":1363,"slug":1364,"type":15},"Code Review","code-review",{"name":1292,"slug":1293,"type":15},{"name":1367,"slug":1368,"type":15},"Pull Requests","pull-requests","2026-07-14T05:26:01.226578",{"slug":1371,"name":1371,"fn":1372,"description":1373,"org":1374,"tags":1375,"stars":1269,"repoUrl":1270,"updatedAt":1378},"mcore-testing","run and manage Megatron-LM tests","Test system for Megatron-LM. Covers test layout, recipe YAML structure, adding and running unit and functional tests, golden values, marker filters, and CI parity.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1376,1377],{"name":1343,"slug":1344,"type":15},{"name":1186,"slug":1187,"type":15},"2026-07-14T05:25:54.928983",{"slug":1380,"name":1380,"fn":1381,"description":1382,"org":1383,"tags":1384,"stars":1269,"repoUrl":1270,"updatedAt":1387},"nightly-sync","manage nightly main-to-dev sync workflows","Domain knowledge for the nightly main-to-dev sync workflow. Covers merge strategy, CI architecture, failure investigation, and known issues.",{"slug":8,"name":9,"logoUrl":10,"githubOrg":9},[1385,1386],{"name":1196,"slug":1197,"type":15},{"name":1279,"slug":1280,"type":15},"2026-07-30T05:29:03.275638",525]